1 /* 2 * Configuation settings for the Freescale MCF5475 board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5475EVB_H 15 #define _M5475EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_HW_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 27 28 /* Command line configuration */ 29 #undef CONFIG_CMD_DATE 30 #define CONFIG_CMD_PCI 31 #define CONFIG_CMD_REGINFO 32 33 #define CONFIG_SLTTMR 34 35 #define CONFIG_FSLDMAFEC 36 #ifdef CONFIG_FSLDMAFEC 37 # define CONFIG_MII 1 38 # define CONFIG_MII_INIT 1 39 # define CONFIG_HAS_ETH1 40 41 # define CONFIG_SYS_DMA_USE_INTSRAM 1 42 # define CONFIG_SYS_DISCOVER_PHY 43 # define CONFIG_SYS_RX_ETH_BUFFER 32 44 # define CONFIG_SYS_TX_ETH_BUFFER 48 45 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 46 47 # define CONFIG_SYS_FEC0_PINMUX 0 48 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 49 # define CONFIG_SYS_FEC1_PINMUX 0 50 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 51 52 # define MCFFEC_TOUT_LOOP 50000 53 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 54 # ifndef CONFIG_SYS_DISCOVER_PHY 55 # define FECDUPLEX FULL 56 # define FECSPEED _100BASET 57 # else 58 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 59 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 60 # endif 61 # endif /* CONFIG_SYS_DISCOVER_PHY */ 62 63 # define CONFIG_IPADDR 192.162.1.2 64 # define CONFIG_NETMASK 255.255.255.0 65 # define CONFIG_SERVERIP 192.162.1.1 66 # define CONFIG_GATEWAYIP 192.162.1.1 67 68 #endif 69 70 #ifdef CONFIG_CMD_USB 71 # define CONFIG_USB_OHCI_NEW 72 73 # ifndef CONFIG_CMD_PCI 74 # define CONFIG_CMD_PCI 75 # endif 76 # define CONFIG_PCI_OHCI 77 78 # undef CONFIG_SYS_USB_OHCI_BOARD_INIT 79 # undef CONFIG_SYS_USB_OHCI_CPU_INIT 80 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 81 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 82 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 83 #endif 84 85 /* I2C */ 86 #define CONFIG_SYS_I2C 87 #define CONFIG_SYS_I2C_FSL 88 #define CONFIG_SYS_FSL_I2C_SPEED 80000 89 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 90 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 91 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 92 93 /* PCI */ 94 #ifdef CONFIG_CMD_PCI 95 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 96 97 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 98 99 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 100 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 101 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 102 103 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 104 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 105 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 106 107 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 108 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 109 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 110 #endif 111 112 #define CONFIG_UDP_CHECKSUM 113 114 #ifdef CONFIG_MCFFEC 115 # define CONFIG_IPADDR 192.162.1.2 116 # define CONFIG_NETMASK 255.255.255.0 117 # define CONFIG_SERVERIP 192.162.1.1 118 # define CONFIG_GATEWAYIP 192.162.1.1 119 #endif /* FEC_ENET */ 120 121 #define CONFIG_HOSTNAME M547xEVB 122 #define CONFIG_EXTRA_ENV_SETTINGS \ 123 "netdev=eth0\0" \ 124 "loadaddr=10000\0" \ 125 "u-boot=u-boot.bin\0" \ 126 "load=tftp ${loadaddr) ${u-boot}\0" \ 127 "upd=run load; run prog\0" \ 128 "prog=prot off bank 1;" \ 129 "era ff800000 ff83ffff;" \ 130 "cp.b ${loadaddr} ff800000 ${filesize};"\ 131 "save\0" \ 132 "" 133 134 #define CONFIG_PRAM 512 /* 512 KB */ 135 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 136 137 #ifdef CONFIG_CMD_KGDB 138 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 139 #else 140 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 141 #endif 142 143 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 144 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 145 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 146 #define CONFIG_SYS_LOAD_ADDR 0x00010000 147 148 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 149 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 150 151 #define CONFIG_SYS_MBAR 0xF0000000 152 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 153 #define CONFIG_SYS_INTSRAMSZ 0x8000 154 155 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 156 157 /* 158 * Low Level Configuration Settings 159 * (address mappings, register initial values, etc.) 160 * You should know what you are doing if you make changes here. 161 */ 162 /*----------------------------------------------------------------------- 163 * Definitions for initial stack pointer and data area (in DPRAM) 164 */ 165 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 166 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 167 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 168 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 169 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 170 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 171 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 172 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 173 174 /*----------------------------------------------------------------------- 175 * Start addresses for the final memory configuration 176 * (Set up by the startup code) 177 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 178 */ 179 #define CONFIG_SYS_SDRAM_BASE 0x00000000 180 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 181 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 182 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 183 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 184 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 185 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 186 #ifdef CONFIG_SYS_DRAMSZ1 187 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 188 #else 189 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 190 #endif 191 192 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 193 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 194 195 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 196 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 197 198 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 199 200 /* Reserve 256 kB for malloc() */ 201 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 202 /* 203 * For booting Linux, the board info and command line data 204 * have to be in the first 8 MB of memory, since this is 205 * the maximum mapped by the Linux kernel during initialization ?? 206 */ 207 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 208 209 /*----------------------------------------------------------------------- 210 * FLASH organization 211 */ 212 #define CONFIG_SYS_FLASH_CFI 213 #ifdef CONFIG_SYS_FLASH_CFI 214 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 215 # define CONFIG_FLASH_CFI_DRIVER 1 216 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 217 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 218 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 219 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 220 #ifdef CONFIG_SYS_NOR1SZ 221 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 222 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 223 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 224 #else 225 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 226 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 227 #endif 228 #endif 229 230 /* Configuration for environment 231 * Environment is not embedded in u-boot but at offset 0x40000 on the flash. 232 * First time runing may have env crc error warning if there is 233 * no correct environment on the flash. 234 */ 235 #define CONFIG_ENV_OFFSET 0x40000 236 #define CONFIG_ENV_SECT_SIZE 0x10000 237 #define CONFIG_ENV_IS_IN_FLASH 1 238 239 /*----------------------------------------------------------------------- 240 * Cache Configuration 241 */ 242 #define CONFIG_SYS_CACHELINE_SIZE 16 243 244 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 245 CONFIG_SYS_INIT_RAM_SIZE - 8) 246 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 247 CONFIG_SYS_INIT_RAM_SIZE - 4) 248 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 249 CF_CACR_IDCM) 250 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 251 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 252 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 253 CF_ACR_EN | CF_ACR_SM_ALL) 254 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 255 CF_CACR_IEC | CF_CACR_ICINVA) 256 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 257 CF_CACR_DEC | CF_CACR_DDCM_P | \ 258 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 259 260 /*----------------------------------------------------------------------- 261 * Chipselect bank definitions 262 */ 263 /* 264 * CS0 - NOR Flash 1, 2, 4, or 8MB 265 * CS1 - NOR Flash 266 * CS2 - Available 267 * CS3 - Available 268 * CS4 - Available 269 * CS5 - Available 270 */ 271 #define CONFIG_SYS_CS0_BASE 0xFF800000 272 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 273 #define CONFIG_SYS_CS0_CTRL 0x00101980 274 275 #ifdef CONFIG_SYS_NOR1SZ 276 #define CONFIG_SYS_CS1_BASE 0xE0000000 277 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 278 #define CONFIG_SYS_CS1_CTRL 0x00101D80 279 #endif 280 281 #endif /* _M5475EVB_H */ 282