1 /* 2 * Configuation settings for the Freescale MCF5475 board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5475EVB_H 15 #define _M5475EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_DISPLAY_BOARDINFO 23 24 #define CONFIG_MCFUART 25 #define CONFIG_SYS_UART_PORT (0) 26 #define CONFIG_BAUDRATE 115200 27 28 #undef CONFIG_HW_WATCHDOG 29 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 30 31 /* Command line configuration */ 32 #include <config_cmd_default.h> 33 34 #define CONFIG_CMD_CACHE 35 #undef CONFIG_CMD_DATE 36 #define CONFIG_CMD_ELF 37 #define CONFIG_CMD_FLASH 38 #define CONFIG_CMD_I2C 39 #define CONFIG_CMD_MEMORY 40 #define CONFIG_CMD_MISC 41 #define CONFIG_CMD_MII 42 #define CONFIG_CMD_PCI 43 #define CONFIG_CMD_PING 44 #define CONFIG_CMD_REGINFO 45 #define CONFIG_CMD_USB 46 47 #define CONFIG_SLTTMR 48 49 #define CONFIG_FSLDMAFEC 50 #ifdef CONFIG_FSLDMAFEC 51 # define CONFIG_MII 1 52 # define CONFIG_MII_INIT 1 53 # define CONFIG_HAS_ETH1 54 55 # define CONFIG_SYS_DMA_USE_INTSRAM 1 56 # define CONFIG_SYS_DISCOVER_PHY 57 # define CONFIG_SYS_RX_ETH_BUFFER 32 58 # define CONFIG_SYS_TX_ETH_BUFFER 48 59 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 60 61 # define CONFIG_SYS_FEC0_PINMUX 0 62 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 63 # define CONFIG_SYS_FEC1_PINMUX 0 64 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 65 66 # define MCFFEC_TOUT_LOOP 50000 67 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 68 # ifndef CONFIG_SYS_DISCOVER_PHY 69 # define FECDUPLEX FULL 70 # define FECSPEED _100BASET 71 # else 72 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 73 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 74 # endif 75 # endif /* CONFIG_SYS_DISCOVER_PHY */ 76 77 # define CONFIG_IPADDR 192.162.1.2 78 # define CONFIG_NETMASK 255.255.255.0 79 # define CONFIG_SERVERIP 192.162.1.1 80 # define CONFIG_GATEWAYIP 192.162.1.1 81 82 #endif 83 84 #ifdef CONFIG_CMD_USB 85 # define CONFIG_USB_OHCI_NEW 86 # define CONFIG_USB_STORAGE 87 88 # ifndef CONFIG_CMD_PCI 89 # define CONFIG_CMD_PCI 90 # endif 91 # define CONFIG_PCI_OHCI 92 # define CONFIG_DOS_PARTITION 93 94 # undef CONFIG_SYS_USB_OHCI_BOARD_INIT 95 # undef CONFIG_SYS_USB_OHCI_CPU_INIT 96 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 97 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 98 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 99 #endif 100 101 /* I2C */ 102 #define CONFIG_SYS_I2C 103 #define CONFIG_SYS_I2C_FSL 104 #define CONFIG_SYS_FSL_I2C_SPEED 80000 105 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 106 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 107 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 108 109 /* PCI */ 110 #ifdef CONFIG_CMD_PCI 111 #define CONFIG_PCI 1 112 #define CONFIG_PCI_PNP 1 113 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 114 115 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 116 117 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 118 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 119 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 120 121 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 122 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 123 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 124 125 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 126 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 127 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 128 #endif 129 130 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 131 #define CONFIG_UDP_CHECKSUM 132 133 #ifdef CONFIG_MCFFEC 134 # define CONFIG_IPADDR 192.162.1.2 135 # define CONFIG_NETMASK 255.255.255.0 136 # define CONFIG_SERVERIP 192.162.1.1 137 # define CONFIG_GATEWAYIP 192.162.1.1 138 #endif /* FEC_ENET */ 139 140 #define CONFIG_HOSTNAME M547xEVB 141 #define CONFIG_EXTRA_ENV_SETTINGS \ 142 "netdev=eth0\0" \ 143 "loadaddr=10000\0" \ 144 "u-boot=u-boot.bin\0" \ 145 "load=tftp ${loadaddr) ${u-boot}\0" \ 146 "upd=run load; run prog\0" \ 147 "prog=prot off bank 1;" \ 148 "era ff800000 ff83ffff;" \ 149 "cp.b ${loadaddr} ff800000 ${filesize};"\ 150 "save\0" \ 151 "" 152 153 #define CONFIG_PRAM 512 /* 512 KB */ 154 #define CONFIG_SYS_PROMPT "-> " 155 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 156 157 #ifdef CONFIG_CMD_KGDB 158 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 159 #else 160 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 161 #endif 162 163 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 164 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 165 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 166 #define CONFIG_SYS_LOAD_ADDR 0x00010000 167 168 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 169 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 170 171 #define CONFIG_SYS_MBAR 0xF0000000 172 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 173 #define CONFIG_SYS_INTSRAMSZ 0x8000 174 175 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 176 177 /* 178 * Low Level Configuration Settings 179 * (address mappings, register initial values, etc.) 180 * You should know what you are doing if you make changes here. 181 */ 182 /*----------------------------------------------------------------------- 183 * Definitions for initial stack pointer and data area (in DPRAM) 184 */ 185 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 186 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 187 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 188 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 189 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 190 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 191 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 192 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 193 194 /*----------------------------------------------------------------------- 195 * Start addresses for the final memory configuration 196 * (Set up by the startup code) 197 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 198 */ 199 #define CONFIG_SYS_SDRAM_BASE 0x00000000 200 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 201 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 202 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 203 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 204 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 205 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 206 #ifdef CONFIG_SYS_DRAMSZ1 207 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 208 #else 209 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 210 #endif 211 212 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 213 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 214 215 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 216 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 217 218 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 219 220 /* Reserve 256 kB for malloc() */ 221 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 222 /* 223 * For booting Linux, the board info and command line data 224 * have to be in the first 8 MB of memory, since this is 225 * the maximum mapped by the Linux kernel during initialization ?? 226 */ 227 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 228 229 /*----------------------------------------------------------------------- 230 * FLASH organization 231 */ 232 #define CONFIG_SYS_FLASH_CFI 233 #ifdef CONFIG_SYS_FLASH_CFI 234 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 235 # define CONFIG_FLASH_CFI_DRIVER 1 236 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 237 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 238 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 239 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 240 #ifdef CONFIG_SYS_NOR1SZ 241 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 242 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 243 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 244 #else 245 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 246 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 247 #endif 248 #endif 249 250 /* Configuration for environment 251 * Environment is not embedded in u-boot but at offset 0x40000 on the flash. 252 * First time runing may have env crc error warning if there is 253 * no correct environment on the flash. 254 */ 255 #define CONFIG_ENV_OFFSET 0x40000 256 #define CONFIG_ENV_SECT_SIZE 0x10000 257 #define CONFIG_ENV_IS_IN_FLASH 1 258 259 /*----------------------------------------------------------------------- 260 * Cache Configuration 261 */ 262 #define CONFIG_SYS_CACHELINE_SIZE 16 263 264 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 265 CONFIG_SYS_INIT_RAM_SIZE - 8) 266 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 267 CONFIG_SYS_INIT_RAM_SIZE - 4) 268 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 269 CF_CACR_IDCM) 270 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 271 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 272 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 273 CF_ACR_EN | CF_ACR_SM_ALL) 274 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 275 CF_CACR_IEC | CF_CACR_ICINVA) 276 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 277 CF_CACR_DEC | CF_CACR_DDCM_P | \ 278 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 279 280 /*----------------------------------------------------------------------- 281 * Chipselect bank definitions 282 */ 283 /* 284 * CS0 - NOR Flash 1, 2, 4, or 8MB 285 * CS1 - NOR Flash 286 * CS2 - Available 287 * CS3 - Available 288 * CS4 - Available 289 * CS5 - Available 290 */ 291 #define CONFIG_SYS_CS0_BASE 0xFF800000 292 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 293 #define CONFIG_SYS_CS0_CTRL 0x00101980 294 295 #ifdef CONFIG_SYS_NOR1SZ 296 #define CONFIG_SYS_CS1_BASE 0xE0000000 297 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 298 #define CONFIG_SYS_CS1_CTRL 0x00101D80 299 #endif 300 301 #endif /* _M5475EVB_H */ 302