1 /* 2 * Configuation settings for the Freescale MCF5475 board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5475EVB_H 15 #define _M5475EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_HW_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 27 28 #define CONFIG_SLTTMR 29 30 #define CONFIG_FSLDMAFEC 31 #ifdef CONFIG_FSLDMAFEC 32 # define CONFIG_MII 1 33 # define CONFIG_MII_INIT 1 34 # define CONFIG_HAS_ETH1 35 36 # define CONFIG_SYS_DMA_USE_INTSRAM 1 37 # define CONFIG_SYS_DISCOVER_PHY 38 # define CONFIG_SYS_RX_ETH_BUFFER 32 39 # define CONFIG_SYS_TX_ETH_BUFFER 48 40 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 41 42 # define CONFIG_SYS_FEC0_PINMUX 0 43 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 44 # define CONFIG_SYS_FEC1_PINMUX 0 45 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 46 47 # define MCFFEC_TOUT_LOOP 50000 48 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 49 # ifndef CONFIG_SYS_DISCOVER_PHY 50 # define FECDUPLEX FULL 51 # define FECSPEED _100BASET 52 # else 53 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 54 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 55 # endif 56 # endif /* CONFIG_SYS_DISCOVER_PHY */ 57 58 # define CONFIG_IPADDR 192.162.1.2 59 # define CONFIG_NETMASK 255.255.255.0 60 # define CONFIG_SERVERIP 192.162.1.1 61 # define CONFIG_GATEWAYIP 192.162.1.1 62 63 #endif 64 65 #ifdef CONFIG_CMD_USB 66 # define CONFIG_USB_OHCI_NEW 67 68 # define CONFIG_PCI_OHCI 69 70 # undef CONFIG_SYS_USB_OHCI_BOARD_INIT 71 # undef CONFIG_SYS_USB_OHCI_CPU_INIT 72 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 73 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 74 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 75 #endif 76 77 /* I2C */ 78 #define CONFIG_SYS_I2C 79 #define CONFIG_SYS_I2C_FSL 80 #define CONFIG_SYS_FSL_I2C_SPEED 80000 81 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 82 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 83 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 84 85 /* PCI */ 86 #ifdef CONFIG_CMD_PCI 87 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 88 89 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 90 91 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 92 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 93 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 94 95 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 96 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 97 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 98 99 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 100 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 101 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 102 #endif 103 104 #define CONFIG_UDP_CHECKSUM 105 106 #ifdef CONFIG_MCFFEC 107 # define CONFIG_IPADDR 192.162.1.2 108 # define CONFIG_NETMASK 255.255.255.0 109 # define CONFIG_SERVERIP 192.162.1.1 110 # define CONFIG_GATEWAYIP 192.162.1.1 111 #endif /* FEC_ENET */ 112 113 #define CONFIG_HOSTNAME M547xEVB 114 #define CONFIG_EXTRA_ENV_SETTINGS \ 115 "netdev=eth0\0" \ 116 "loadaddr=10000\0" \ 117 "u-boot=u-boot.bin\0" \ 118 "load=tftp ${loadaddr) ${u-boot}\0" \ 119 "upd=run load; run prog\0" \ 120 "prog=prot off bank 1;" \ 121 "era ff800000 ff83ffff;" \ 122 "cp.b ${loadaddr} ff800000 ${filesize};"\ 123 "save\0" \ 124 "" 125 126 #define CONFIG_PRAM 512 /* 512 KB */ 127 128 #define CONFIG_SYS_LOAD_ADDR 0x00010000 129 130 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 131 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 132 133 #define CONFIG_SYS_MBAR 0xF0000000 134 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 135 #define CONFIG_SYS_INTSRAMSZ 0x8000 136 137 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 138 139 /* 140 * Low Level Configuration Settings 141 * (address mappings, register initial values, etc.) 142 * You should know what you are doing if you make changes here. 143 */ 144 /*----------------------------------------------------------------------- 145 * Definitions for initial stack pointer and data area (in DPRAM) 146 */ 147 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 148 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 149 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 150 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 151 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 152 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 153 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 154 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 155 156 /*----------------------------------------------------------------------- 157 * Start addresses for the final memory configuration 158 * (Set up by the startup code) 159 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 160 */ 161 #define CONFIG_SYS_SDRAM_BASE 0x00000000 162 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 163 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 164 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 165 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 166 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 167 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 168 #ifdef CONFIG_SYS_DRAMSZ1 169 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 170 #else 171 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 172 #endif 173 174 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 175 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 176 177 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 178 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 179 180 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 181 182 /* Reserve 256 kB for malloc() */ 183 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 184 /* 185 * For booting Linux, the board info and command line data 186 * have to be in the first 8 MB of memory, since this is 187 * the maximum mapped by the Linux kernel during initialization ?? 188 */ 189 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 190 191 /*----------------------------------------------------------------------- 192 * FLASH organization 193 */ 194 #define CONFIG_SYS_FLASH_CFI 195 #ifdef CONFIG_SYS_FLASH_CFI 196 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 197 # define CONFIG_FLASH_CFI_DRIVER 1 198 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 199 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 200 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 201 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 202 #ifdef CONFIG_SYS_NOR1SZ 203 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 204 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 205 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 206 #else 207 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 208 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 209 #endif 210 #endif 211 212 /* Configuration for environment 213 * Environment is not embedded in u-boot but at offset 0x40000 on the flash. 214 * First time runing may have env crc error warning if there is 215 * no correct environment on the flash. 216 */ 217 #define CONFIG_ENV_OFFSET 0x40000 218 #define CONFIG_ENV_SECT_SIZE 0x10000 219 220 /*----------------------------------------------------------------------- 221 * Cache Configuration 222 */ 223 #define CONFIG_SYS_CACHELINE_SIZE 16 224 225 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 226 CONFIG_SYS_INIT_RAM_SIZE - 8) 227 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 228 CONFIG_SYS_INIT_RAM_SIZE - 4) 229 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 230 CF_CACR_IDCM) 231 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 232 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 233 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 234 CF_ACR_EN | CF_ACR_SM_ALL) 235 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 236 CF_CACR_IEC | CF_CACR_ICINVA) 237 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 238 CF_CACR_DEC | CF_CACR_DDCM_P | \ 239 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 240 241 /*----------------------------------------------------------------------- 242 * Chipselect bank definitions 243 */ 244 /* 245 * CS0 - NOR Flash 1, 2, 4, or 8MB 246 * CS1 - NOR Flash 247 * CS2 - Available 248 * CS3 - Available 249 * CS4 - Available 250 * CS5 - Available 251 */ 252 #define CONFIG_SYS_CS0_BASE 0xFF800000 253 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 254 #define CONFIG_SYS_CS0_CTRL 0x00101980 255 256 #ifdef CONFIG_SYS_NOR1SZ 257 #define CONFIG_SYS_CS1_BASE 0xE0000000 258 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 259 #define CONFIG_SYS_CS1_CTRL 0x00101D80 260 #endif 261 262 #endif /* _M5475EVB_H */ 263