1 /* 2 * Configuation settings for the Freescale MCF5475 board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5475EVB_H 15 #define _M5475EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_HW_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 27 28 /* Command line configuration */ 29 #define CONFIG_CMD_PCI 30 #define CONFIG_CMD_REGINFO 31 32 #define CONFIG_SLTTMR 33 34 #define CONFIG_FSLDMAFEC 35 #ifdef CONFIG_FSLDMAFEC 36 # define CONFIG_MII 1 37 # define CONFIG_MII_INIT 1 38 # define CONFIG_HAS_ETH1 39 40 # define CONFIG_SYS_DMA_USE_INTSRAM 1 41 # define CONFIG_SYS_DISCOVER_PHY 42 # define CONFIG_SYS_RX_ETH_BUFFER 32 43 # define CONFIG_SYS_TX_ETH_BUFFER 48 44 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 45 46 # define CONFIG_SYS_FEC0_PINMUX 0 47 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 48 # define CONFIG_SYS_FEC1_PINMUX 0 49 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 50 51 # define MCFFEC_TOUT_LOOP 50000 52 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 53 # ifndef CONFIG_SYS_DISCOVER_PHY 54 # define FECDUPLEX FULL 55 # define FECSPEED _100BASET 56 # else 57 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 58 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 59 # endif 60 # endif /* CONFIG_SYS_DISCOVER_PHY */ 61 62 # define CONFIG_IPADDR 192.162.1.2 63 # define CONFIG_NETMASK 255.255.255.0 64 # define CONFIG_SERVERIP 192.162.1.1 65 # define CONFIG_GATEWAYIP 192.162.1.1 66 67 #endif 68 69 #ifdef CONFIG_CMD_USB 70 # define CONFIG_USB_OHCI_NEW 71 72 # ifndef CONFIG_CMD_PCI 73 # define CONFIG_CMD_PCI 74 # endif 75 # define CONFIG_PCI_OHCI 76 77 # undef CONFIG_SYS_USB_OHCI_BOARD_INIT 78 # undef CONFIG_SYS_USB_OHCI_CPU_INIT 79 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 80 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 81 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 82 #endif 83 84 /* I2C */ 85 #define CONFIG_SYS_I2C 86 #define CONFIG_SYS_I2C_FSL 87 #define CONFIG_SYS_FSL_I2C_SPEED 80000 88 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 89 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 90 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 91 92 /* PCI */ 93 #ifdef CONFIG_CMD_PCI 94 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 95 96 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 97 98 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 99 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 100 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 101 102 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 103 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 104 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 105 106 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 107 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 108 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 109 #endif 110 111 #define CONFIG_UDP_CHECKSUM 112 113 #ifdef CONFIG_MCFFEC 114 # define CONFIG_IPADDR 192.162.1.2 115 # define CONFIG_NETMASK 255.255.255.0 116 # define CONFIG_SERVERIP 192.162.1.1 117 # define CONFIG_GATEWAYIP 192.162.1.1 118 #endif /* FEC_ENET */ 119 120 #define CONFIG_HOSTNAME M547xEVB 121 #define CONFIG_EXTRA_ENV_SETTINGS \ 122 "netdev=eth0\0" \ 123 "loadaddr=10000\0" \ 124 "u-boot=u-boot.bin\0" \ 125 "load=tftp ${loadaddr) ${u-boot}\0" \ 126 "upd=run load; run prog\0" \ 127 "prog=prot off bank 1;" \ 128 "era ff800000 ff83ffff;" \ 129 "cp.b ${loadaddr} ff800000 ${filesize};"\ 130 "save\0" \ 131 "" 132 133 #define CONFIG_PRAM 512 /* 512 KB */ 134 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 135 136 #ifdef CONFIG_CMD_KGDB 137 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 138 #else 139 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 140 #endif 141 142 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 143 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 144 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 145 #define CONFIG_SYS_LOAD_ADDR 0x00010000 146 147 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 148 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 149 150 #define CONFIG_SYS_MBAR 0xF0000000 151 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 152 #define CONFIG_SYS_INTSRAMSZ 0x8000 153 154 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 155 156 /* 157 * Low Level Configuration Settings 158 * (address mappings, register initial values, etc.) 159 * You should know what you are doing if you make changes here. 160 */ 161 /*----------------------------------------------------------------------- 162 * Definitions for initial stack pointer and data area (in DPRAM) 163 */ 164 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 165 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 166 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 167 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 168 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 169 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 170 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 171 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 172 173 /*----------------------------------------------------------------------- 174 * Start addresses for the final memory configuration 175 * (Set up by the startup code) 176 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 177 */ 178 #define CONFIG_SYS_SDRAM_BASE 0x00000000 179 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 180 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 181 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 182 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 183 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 184 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 185 #ifdef CONFIG_SYS_DRAMSZ1 186 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 187 #else 188 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 189 #endif 190 191 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 192 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 193 194 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 195 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 196 197 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 198 199 /* Reserve 256 kB for malloc() */ 200 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 201 /* 202 * For booting Linux, the board info and command line data 203 * have to be in the first 8 MB of memory, since this is 204 * the maximum mapped by the Linux kernel during initialization ?? 205 */ 206 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 207 208 /*----------------------------------------------------------------------- 209 * FLASH organization 210 */ 211 #define CONFIG_SYS_FLASH_CFI 212 #ifdef CONFIG_SYS_FLASH_CFI 213 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 214 # define CONFIG_FLASH_CFI_DRIVER 1 215 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 216 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 217 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 218 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 219 #ifdef CONFIG_SYS_NOR1SZ 220 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 221 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 222 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 223 #else 224 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 225 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 226 #endif 227 #endif 228 229 /* Configuration for environment 230 * Environment is not embedded in u-boot but at offset 0x40000 on the flash. 231 * First time runing may have env crc error warning if there is 232 * no correct environment on the flash. 233 */ 234 #define CONFIG_ENV_OFFSET 0x40000 235 #define CONFIG_ENV_SECT_SIZE 0x10000 236 #define CONFIG_ENV_IS_IN_FLASH 1 237 238 /*----------------------------------------------------------------------- 239 * Cache Configuration 240 */ 241 #define CONFIG_SYS_CACHELINE_SIZE 16 242 243 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 244 CONFIG_SYS_INIT_RAM_SIZE - 8) 245 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 246 CONFIG_SYS_INIT_RAM_SIZE - 4) 247 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 248 CF_CACR_IDCM) 249 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 250 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 251 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 252 CF_ACR_EN | CF_ACR_SM_ALL) 253 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 254 CF_CACR_IEC | CF_CACR_ICINVA) 255 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 256 CF_CACR_DEC | CF_CACR_DDCM_P | \ 257 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 258 259 /*----------------------------------------------------------------------- 260 * Chipselect bank definitions 261 */ 262 /* 263 * CS0 - NOR Flash 1, 2, 4, or 8MB 264 * CS1 - NOR Flash 265 * CS2 - Available 266 * CS3 - Available 267 * CS4 - Available 268 * CS5 - Available 269 */ 270 #define CONFIG_SYS_CS0_BASE 0xFF800000 271 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 272 #define CONFIG_SYS_CS0_CTRL 0x00101980 273 274 #ifdef CONFIG_SYS_NOR1SZ 275 #define CONFIG_SYS_CS1_BASE 0xE0000000 276 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 277 #define CONFIG_SYS_CS1_CTRL 0x00101D80 278 #endif 279 280 #endif /* _M5475EVB_H */ 281