1 /* 2 * Configuation settings for the Freescale MCF5475 board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5475EVB_H 15 #define _M5475EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_DISPLAY_BOARDINFO 23 24 #define CONFIG_MCFUART 25 #define CONFIG_SYS_UART_PORT (0) 26 #define CONFIG_BAUDRATE 115200 27 28 #undef CONFIG_HW_WATCHDOG 29 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 30 31 /* Command line configuration */ 32 #define CONFIG_CMD_CACHE 33 #undef CONFIG_CMD_DATE 34 #define CONFIG_CMD_I2C 35 #define CONFIG_CMD_MII 36 #define CONFIG_CMD_PCI 37 #define CONFIG_CMD_PING 38 #define CONFIG_CMD_REGINFO 39 #define CONFIG_CMD_USB 40 41 #define CONFIG_SLTTMR 42 43 #define CONFIG_FSLDMAFEC 44 #ifdef CONFIG_FSLDMAFEC 45 # define CONFIG_MII 1 46 # define CONFIG_MII_INIT 1 47 # define CONFIG_HAS_ETH1 48 49 # define CONFIG_SYS_DMA_USE_INTSRAM 1 50 # define CONFIG_SYS_DISCOVER_PHY 51 # define CONFIG_SYS_RX_ETH_BUFFER 32 52 # define CONFIG_SYS_TX_ETH_BUFFER 48 53 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 54 55 # define CONFIG_SYS_FEC0_PINMUX 0 56 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 57 # define CONFIG_SYS_FEC1_PINMUX 0 58 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 59 60 # define MCFFEC_TOUT_LOOP 50000 61 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 62 # ifndef CONFIG_SYS_DISCOVER_PHY 63 # define FECDUPLEX FULL 64 # define FECSPEED _100BASET 65 # else 66 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 67 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 68 # endif 69 # endif /* CONFIG_SYS_DISCOVER_PHY */ 70 71 # define CONFIG_IPADDR 192.162.1.2 72 # define CONFIG_NETMASK 255.255.255.0 73 # define CONFIG_SERVERIP 192.162.1.1 74 # define CONFIG_GATEWAYIP 192.162.1.1 75 76 #endif 77 78 #ifdef CONFIG_CMD_USB 79 # define CONFIG_USB_OHCI_NEW 80 # define CONFIG_USB_STORAGE 81 82 # ifndef CONFIG_CMD_PCI 83 # define CONFIG_CMD_PCI 84 # endif 85 # define CONFIG_PCI_OHCI 86 # define CONFIG_DOS_PARTITION 87 88 # undef CONFIG_SYS_USB_OHCI_BOARD_INIT 89 # undef CONFIG_SYS_USB_OHCI_CPU_INIT 90 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 91 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 92 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 93 #endif 94 95 /* I2C */ 96 #define CONFIG_SYS_I2C 97 #define CONFIG_SYS_I2C_FSL 98 #define CONFIG_SYS_FSL_I2C_SPEED 80000 99 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 100 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 101 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 102 103 /* PCI */ 104 #ifdef CONFIG_CMD_PCI 105 #define CONFIG_PCI 1 106 #define CONFIG_PCI_PNP 1 107 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 108 109 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 110 111 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 112 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 113 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 114 115 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 116 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 117 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 118 119 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 120 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 121 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 122 #endif 123 124 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 125 #define CONFIG_UDP_CHECKSUM 126 127 #ifdef CONFIG_MCFFEC 128 # define CONFIG_IPADDR 192.162.1.2 129 # define CONFIG_NETMASK 255.255.255.0 130 # define CONFIG_SERVERIP 192.162.1.1 131 # define CONFIG_GATEWAYIP 192.162.1.1 132 #endif /* FEC_ENET */ 133 134 #define CONFIG_HOSTNAME M547xEVB 135 #define CONFIG_EXTRA_ENV_SETTINGS \ 136 "netdev=eth0\0" \ 137 "loadaddr=10000\0" \ 138 "u-boot=u-boot.bin\0" \ 139 "load=tftp ${loadaddr) ${u-boot}\0" \ 140 "upd=run load; run prog\0" \ 141 "prog=prot off bank 1;" \ 142 "era ff800000 ff83ffff;" \ 143 "cp.b ${loadaddr} ff800000 ${filesize};"\ 144 "save\0" \ 145 "" 146 147 #define CONFIG_PRAM 512 /* 512 KB */ 148 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 149 150 #ifdef CONFIG_CMD_KGDB 151 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 152 #else 153 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 154 #endif 155 156 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 157 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 158 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 159 #define CONFIG_SYS_LOAD_ADDR 0x00010000 160 161 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 162 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 163 164 #define CONFIG_SYS_MBAR 0xF0000000 165 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 166 #define CONFIG_SYS_INTSRAMSZ 0x8000 167 168 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 169 170 /* 171 * Low Level Configuration Settings 172 * (address mappings, register initial values, etc.) 173 * You should know what you are doing if you make changes here. 174 */ 175 /*----------------------------------------------------------------------- 176 * Definitions for initial stack pointer and data area (in DPRAM) 177 */ 178 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 179 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 180 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 181 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 182 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 183 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 184 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 185 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 186 187 /*----------------------------------------------------------------------- 188 * Start addresses for the final memory configuration 189 * (Set up by the startup code) 190 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 191 */ 192 #define CONFIG_SYS_SDRAM_BASE 0x00000000 193 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 194 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 195 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 196 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 197 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 198 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 199 #ifdef CONFIG_SYS_DRAMSZ1 200 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 201 #else 202 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 203 #endif 204 205 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 206 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 207 208 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 209 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 210 211 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 212 213 /* Reserve 256 kB for malloc() */ 214 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 215 /* 216 * For booting Linux, the board info and command line data 217 * have to be in the first 8 MB of memory, since this is 218 * the maximum mapped by the Linux kernel during initialization ?? 219 */ 220 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 221 222 /*----------------------------------------------------------------------- 223 * FLASH organization 224 */ 225 #define CONFIG_SYS_FLASH_CFI 226 #ifdef CONFIG_SYS_FLASH_CFI 227 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 228 # define CONFIG_FLASH_CFI_DRIVER 1 229 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 230 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 231 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 232 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 233 #ifdef CONFIG_SYS_NOR1SZ 234 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 235 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 236 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 237 #else 238 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 239 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 240 #endif 241 #endif 242 243 /* Configuration for environment 244 * Environment is not embedded in u-boot but at offset 0x40000 on the flash. 245 * First time runing may have env crc error warning if there is 246 * no correct environment on the flash. 247 */ 248 #define CONFIG_ENV_OFFSET 0x40000 249 #define CONFIG_ENV_SECT_SIZE 0x10000 250 #define CONFIG_ENV_IS_IN_FLASH 1 251 252 /*----------------------------------------------------------------------- 253 * Cache Configuration 254 */ 255 #define CONFIG_SYS_CACHELINE_SIZE 16 256 257 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 258 CONFIG_SYS_INIT_RAM_SIZE - 8) 259 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 260 CONFIG_SYS_INIT_RAM_SIZE - 4) 261 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 262 CF_CACR_IDCM) 263 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 264 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 265 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 266 CF_ACR_EN | CF_ACR_SM_ALL) 267 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 268 CF_CACR_IEC | CF_CACR_ICINVA) 269 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 270 CF_CACR_DEC | CF_CACR_DDCM_P | \ 271 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 272 273 /*----------------------------------------------------------------------- 274 * Chipselect bank definitions 275 */ 276 /* 277 * CS0 - NOR Flash 1, 2, 4, or 8MB 278 * CS1 - NOR Flash 279 * CS2 - Available 280 * CS3 - Available 281 * CS4 - Available 282 * CS5 - Available 283 */ 284 #define CONFIG_SYS_CS0_BASE 0xFF800000 285 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 286 #define CONFIG_SYS_CS0_CTRL 0x00101980 287 288 #ifdef CONFIG_SYS_NOR1SZ 289 #define CONFIG_SYS_CS1_BASE 0xE0000000 290 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 291 #define CONFIG_SYS_CS1_CTRL 0x00101D80 292 #endif 293 294 #endif /* _M5475EVB_H */ 295