1 /* 2 * Configuation settings for the Freescale MCF5475 board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5475EVB_H 15 #define _M5475EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_MCF547x_8x /* define processor family */ 22 #define CONFIG_M547x /* define processor type */ 23 #define CONFIG_M5475 /* define processor type */ 24 25 #define CONFIG_DISPLAY_BOARDINFO 26 27 #define CONFIG_MCFUART 28 #define CONFIG_SYS_UART_PORT (0) 29 #define CONFIG_BAUDRATE 115200 30 31 #undef CONFIG_HW_WATCHDOG 32 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 33 34 /* Command line configuration */ 35 #include <config_cmd_default.h> 36 37 #define CONFIG_CMD_CACHE 38 #undef CONFIG_CMD_DATE 39 #define CONFIG_CMD_ELF 40 #define CONFIG_CMD_FLASH 41 #define CONFIG_CMD_I2C 42 #define CONFIG_CMD_MEMORY 43 #define CONFIG_CMD_MISC 44 #define CONFIG_CMD_MII 45 #define CONFIG_CMD_NET 46 #define CONFIG_CMD_PCI 47 #define CONFIG_CMD_PING 48 #define CONFIG_CMD_REGINFO 49 #define CONFIG_CMD_USB 50 51 #define CONFIG_SLTTMR 52 53 #define CONFIG_FSLDMAFEC 54 #ifdef CONFIG_FSLDMAFEC 55 # define CONFIG_MII 1 56 # define CONFIG_MII_INIT 1 57 # define CONFIG_HAS_ETH1 58 59 # define CONFIG_SYS_DMA_USE_INTSRAM 1 60 # define CONFIG_SYS_DISCOVER_PHY 61 # define CONFIG_SYS_RX_ETH_BUFFER 32 62 # define CONFIG_SYS_TX_ETH_BUFFER 48 63 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 64 65 # define CONFIG_SYS_FEC0_PINMUX 0 66 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 67 # define CONFIG_SYS_FEC1_PINMUX 0 68 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 69 70 # define MCFFEC_TOUT_LOOP 50000 71 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 72 # ifndef CONFIG_SYS_DISCOVER_PHY 73 # define FECDUPLEX FULL 74 # define FECSPEED _100BASET 75 # else 76 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 77 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 78 # endif 79 # endif /* CONFIG_SYS_DISCOVER_PHY */ 80 81 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 82 # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 83 # define CONFIG_IPADDR 192.162.1.2 84 # define CONFIG_NETMASK 255.255.255.0 85 # define CONFIG_SERVERIP 192.162.1.1 86 # define CONFIG_GATEWAYIP 192.162.1.1 87 # define CONFIG_OVERWRITE_ETHADDR_ONCE 88 89 #endif 90 91 #ifdef CONFIG_CMD_USB 92 # define CONFIG_USB_OHCI_NEW 93 # define CONFIG_USB_STORAGE 94 95 # ifndef CONFIG_CMD_PCI 96 # define CONFIG_CMD_PCI 97 # endif 98 # define CONFIG_PCI_OHCI 99 # define CONFIG_DOS_PARTITION 100 101 # undef CONFIG_SYS_USB_OHCI_BOARD_INIT 102 # undef CONFIG_SYS_USB_OHCI_CPU_INIT 103 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 104 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 105 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 106 #endif 107 108 /* I2C */ 109 #define CONFIG_SYS_I2C 110 #define CONFIG_SYS_I2C_FSL 111 #define CONFIG_SYS_FSL_I2C_SPEED 80000 112 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 113 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 114 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 115 116 /* PCI */ 117 #ifdef CONFIG_CMD_PCI 118 #define CONFIG_PCI 1 119 #define CONFIG_PCI_PNP 1 120 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 121 122 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 123 124 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 125 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 126 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 127 128 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 129 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 130 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 131 132 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 133 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 134 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 135 #endif 136 137 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 138 #define CONFIG_UDP_CHECKSUM 139 140 #ifdef CONFIG_MCFFEC 141 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 142 # define CONFIG_IPADDR 192.162.1.2 143 # define CONFIG_NETMASK 255.255.255.0 144 # define CONFIG_SERVERIP 192.162.1.1 145 # define CONFIG_GATEWAYIP 192.162.1.1 146 # define CONFIG_OVERWRITE_ETHADDR_ONCE 147 #endif /* FEC_ENET */ 148 149 #define CONFIG_HOSTNAME M547xEVB 150 #define CONFIG_EXTRA_ENV_SETTINGS \ 151 "netdev=eth0\0" \ 152 "loadaddr=10000\0" \ 153 "u-boot=u-boot.bin\0" \ 154 "load=tftp ${loadaddr) ${u-boot}\0" \ 155 "upd=run load; run prog\0" \ 156 "prog=prot off bank 1;" \ 157 "era ff800000 ff83ffff;" \ 158 "cp.b ${loadaddr} ff800000 ${filesize};"\ 159 "save\0" \ 160 "" 161 162 #define CONFIG_PRAM 512 /* 512 KB */ 163 #define CONFIG_SYS_PROMPT "-> " 164 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 165 166 #ifdef CONFIG_CMD_KGDB 167 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 168 #else 169 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 170 #endif 171 172 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 173 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 174 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 175 #define CONFIG_SYS_LOAD_ADDR 0x00010000 176 177 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 178 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 179 180 #define CONFIG_SYS_MBAR 0xF0000000 181 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 182 #define CONFIG_SYS_INTSRAMSZ 0x8000 183 184 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 185 186 /* 187 * Low Level Configuration Settings 188 * (address mappings, register initial values, etc.) 189 * You should know what you are doing if you make changes here. 190 */ 191 /*----------------------------------------------------------------------- 192 * Definitions for initial stack pointer and data area (in DPRAM) 193 */ 194 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 195 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 196 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 197 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 198 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 199 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 200 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 201 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 202 203 /*----------------------------------------------------------------------- 204 * Start addresses for the final memory configuration 205 * (Set up by the startup code) 206 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 207 */ 208 #define CONFIG_SYS_SDRAM_BASE 0x00000000 209 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 210 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 211 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 212 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 213 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 214 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 215 #ifdef CONFIG_SYS_DRAMSZ1 216 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 217 #else 218 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 219 #endif 220 221 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 222 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 223 224 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 225 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 226 227 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 228 229 /* Reserve 256 kB for malloc() */ 230 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 231 /* 232 * For booting Linux, the board info and command line data 233 * have to be in the first 8 MB of memory, since this is 234 * the maximum mapped by the Linux kernel during initialization ?? 235 */ 236 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 237 238 /*----------------------------------------------------------------------- 239 * FLASH organization 240 */ 241 #define CONFIG_SYS_FLASH_CFI 242 #ifdef CONFIG_SYS_FLASH_CFI 243 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 244 # define CONFIG_FLASH_CFI_DRIVER 1 245 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 246 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 247 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 248 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 249 #ifdef CONFIG_SYS_NOR1SZ 250 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 251 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 252 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 253 #else 254 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 255 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 256 #endif 257 #endif 258 259 /* Configuration for environment 260 * Environment is not embedded in u-boot but at offset 0x40000 on the flash. 261 * First time runing may have env crc error warning if there is 262 * no correct environment on the flash. 263 */ 264 #define CONFIG_ENV_OFFSET 0x40000 265 #define CONFIG_ENV_SECT_SIZE 0x10000 266 #define CONFIG_ENV_IS_IN_FLASH 1 267 268 /*----------------------------------------------------------------------- 269 * Cache Configuration 270 */ 271 #define CONFIG_SYS_CACHELINE_SIZE 16 272 273 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 274 CONFIG_SYS_INIT_RAM_SIZE - 8) 275 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 276 CONFIG_SYS_INIT_RAM_SIZE - 4) 277 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 278 CF_CACR_IDCM) 279 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 280 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 281 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 282 CF_ACR_EN | CF_ACR_SM_ALL) 283 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 284 CF_CACR_IEC | CF_CACR_ICINVA) 285 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 286 CF_CACR_DEC | CF_CACR_DDCM_P | \ 287 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 288 289 /*----------------------------------------------------------------------- 290 * Chipselect bank definitions 291 */ 292 /* 293 * CS0 - NOR Flash 1, 2, 4, or 8MB 294 * CS1 - NOR Flash 295 * CS2 - Available 296 * CS3 - Available 297 * CS4 - Available 298 * CS5 - Available 299 */ 300 #define CONFIG_SYS_CS0_BASE 0xFF800000 301 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 302 #define CONFIG_SYS_CS0_CTRL 0x00101980 303 304 #ifdef CONFIG_SYS_NOR1SZ 305 #define CONFIG_SYS_CS1_BASE 0xE0000000 306 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 307 #define CONFIG_SYS_CS1_CTRL 0x00101D80 308 #endif 309 310 #endif /* _M5475EVB_H */ 311