1 /* 2 * Configuation settings for the Freescale MCF5475 board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5475EVB_H 15 #define _M5475EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_DISPLAY_BOARDINFO 23 24 #define CONFIG_MCFUART 25 #define CONFIG_SYS_UART_PORT (0) 26 #define CONFIG_BAUDRATE 115200 27 28 #undef CONFIG_HW_WATCHDOG 29 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 30 31 /* Command line configuration */ 32 #undef CONFIG_CMD_DATE 33 #define CONFIG_CMD_PCI 34 #define CONFIG_CMD_REGINFO 35 36 #define CONFIG_SLTTMR 37 38 #define CONFIG_FSLDMAFEC 39 #ifdef CONFIG_FSLDMAFEC 40 # define CONFIG_MII 1 41 # define CONFIG_MII_INIT 1 42 # define CONFIG_HAS_ETH1 43 44 # define CONFIG_SYS_DMA_USE_INTSRAM 1 45 # define CONFIG_SYS_DISCOVER_PHY 46 # define CONFIG_SYS_RX_ETH_BUFFER 32 47 # define CONFIG_SYS_TX_ETH_BUFFER 48 48 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 49 50 # define CONFIG_SYS_FEC0_PINMUX 0 51 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 52 # define CONFIG_SYS_FEC1_PINMUX 0 53 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 54 55 # define MCFFEC_TOUT_LOOP 50000 56 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 57 # ifndef CONFIG_SYS_DISCOVER_PHY 58 # define FECDUPLEX FULL 59 # define FECSPEED _100BASET 60 # else 61 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 62 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 63 # endif 64 # endif /* CONFIG_SYS_DISCOVER_PHY */ 65 66 # define CONFIG_IPADDR 192.162.1.2 67 # define CONFIG_NETMASK 255.255.255.0 68 # define CONFIG_SERVERIP 192.162.1.1 69 # define CONFIG_GATEWAYIP 192.162.1.1 70 71 #endif 72 73 #ifdef CONFIG_CMD_USB 74 # define CONFIG_USB_OHCI_NEW 75 76 # ifndef CONFIG_CMD_PCI 77 # define CONFIG_CMD_PCI 78 # endif 79 # define CONFIG_PCI_OHCI 80 # define CONFIG_DOS_PARTITION 81 82 # undef CONFIG_SYS_USB_OHCI_BOARD_INIT 83 # undef CONFIG_SYS_USB_OHCI_CPU_INIT 84 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 85 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 86 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 87 #endif 88 89 /* I2C */ 90 #define CONFIG_SYS_I2C 91 #define CONFIG_SYS_I2C_FSL 92 #define CONFIG_SYS_FSL_I2C_SPEED 80000 93 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 94 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 95 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 96 97 /* PCI */ 98 #ifdef CONFIG_CMD_PCI 99 #define CONFIG_PCI 1 100 #define CONFIG_PCI_PNP 1 101 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 102 103 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 104 105 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 106 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 107 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 108 109 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 110 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 111 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 112 113 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 114 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 115 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 116 #endif 117 118 #define CONFIG_UDP_CHECKSUM 119 120 #ifdef CONFIG_MCFFEC 121 # define CONFIG_IPADDR 192.162.1.2 122 # define CONFIG_NETMASK 255.255.255.0 123 # define CONFIG_SERVERIP 192.162.1.1 124 # define CONFIG_GATEWAYIP 192.162.1.1 125 #endif /* FEC_ENET */ 126 127 #define CONFIG_HOSTNAME M547xEVB 128 #define CONFIG_EXTRA_ENV_SETTINGS \ 129 "netdev=eth0\0" \ 130 "loadaddr=10000\0" \ 131 "u-boot=u-boot.bin\0" \ 132 "load=tftp ${loadaddr) ${u-boot}\0" \ 133 "upd=run load; run prog\0" \ 134 "prog=prot off bank 1;" \ 135 "era ff800000 ff83ffff;" \ 136 "cp.b ${loadaddr} ff800000 ${filesize};"\ 137 "save\0" \ 138 "" 139 140 #define CONFIG_PRAM 512 /* 512 KB */ 141 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 142 143 #ifdef CONFIG_CMD_KGDB 144 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 145 #else 146 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 147 #endif 148 149 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 150 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 151 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 152 #define CONFIG_SYS_LOAD_ADDR 0x00010000 153 154 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 155 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 156 157 #define CONFIG_SYS_MBAR 0xF0000000 158 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 159 #define CONFIG_SYS_INTSRAMSZ 0x8000 160 161 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 162 163 /* 164 * Low Level Configuration Settings 165 * (address mappings, register initial values, etc.) 166 * You should know what you are doing if you make changes here. 167 */ 168 /*----------------------------------------------------------------------- 169 * Definitions for initial stack pointer and data area (in DPRAM) 170 */ 171 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 172 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 173 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 174 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 175 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 176 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 177 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 178 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 179 180 /*----------------------------------------------------------------------- 181 * Start addresses for the final memory configuration 182 * (Set up by the startup code) 183 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 184 */ 185 #define CONFIG_SYS_SDRAM_BASE 0x00000000 186 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 187 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 188 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 189 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 190 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 191 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 192 #ifdef CONFIG_SYS_DRAMSZ1 193 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 194 #else 195 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 196 #endif 197 198 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 199 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 200 201 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 202 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 203 204 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 205 206 /* Reserve 256 kB for malloc() */ 207 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 208 /* 209 * For booting Linux, the board info and command line data 210 * have to be in the first 8 MB of memory, since this is 211 * the maximum mapped by the Linux kernel during initialization ?? 212 */ 213 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 214 215 /*----------------------------------------------------------------------- 216 * FLASH organization 217 */ 218 #define CONFIG_SYS_FLASH_CFI 219 #ifdef CONFIG_SYS_FLASH_CFI 220 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 221 # define CONFIG_FLASH_CFI_DRIVER 1 222 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 223 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 224 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 225 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 226 #ifdef CONFIG_SYS_NOR1SZ 227 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 228 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 229 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 230 #else 231 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 232 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 233 #endif 234 #endif 235 236 /* Configuration for environment 237 * Environment is not embedded in u-boot but at offset 0x40000 on the flash. 238 * First time runing may have env crc error warning if there is 239 * no correct environment on the flash. 240 */ 241 #define CONFIG_ENV_OFFSET 0x40000 242 #define CONFIG_ENV_SECT_SIZE 0x10000 243 #define CONFIG_ENV_IS_IN_FLASH 1 244 245 /*----------------------------------------------------------------------- 246 * Cache Configuration 247 */ 248 #define CONFIG_SYS_CACHELINE_SIZE 16 249 250 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 251 CONFIG_SYS_INIT_RAM_SIZE - 8) 252 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 253 CONFIG_SYS_INIT_RAM_SIZE - 4) 254 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 255 CF_CACR_IDCM) 256 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 257 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 258 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 259 CF_ACR_EN | CF_ACR_SM_ALL) 260 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 261 CF_CACR_IEC | CF_CACR_ICINVA) 262 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 263 CF_CACR_DEC | CF_CACR_DDCM_P | \ 264 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 265 266 /*----------------------------------------------------------------------- 267 * Chipselect bank definitions 268 */ 269 /* 270 * CS0 - NOR Flash 1, 2, 4, or 8MB 271 * CS1 - NOR Flash 272 * CS2 - Available 273 * CS3 - Available 274 * CS4 - Available 275 * CS5 - Available 276 */ 277 #define CONFIG_SYS_CS0_BASE 0xFF800000 278 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 279 #define CONFIG_SYS_CS0_CTRL 0x00101980 280 281 #ifdef CONFIG_SYS_NOR1SZ 282 #define CONFIG_SYS_CS1_BASE 0xE0000000 283 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 284 #define CONFIG_SYS_CS1_CTRL 0x00101D80 285 #endif 286 287 #endif /* _M5475EVB_H */ 288