1 /* 2 * Configuation settings for the Freescale MCF54455 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef _M54455EVB_H 31 #define _M54455EVB_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_MCF5445x /* define processor family */ 38 #define CONFIG_M54455 /* define processor type */ 39 #define CONFIG_M54455EVB /* M54455EVB board */ 40 41 #define CONFIG_MCFUART 42 #define CONFIG_SYS_UART_PORT (0) 43 #define CONFIG_BAUDRATE 115200 44 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 45 46 #undef CONFIG_WATCHDOG 47 48 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 49 50 /* 51 * BOOTP options 52 */ 53 #define CONFIG_BOOTP_BOOTFILESIZE 54 #define CONFIG_BOOTP_BOOTPATH 55 #define CONFIG_BOOTP_GATEWAY 56 #define CONFIG_BOOTP_HOSTNAME 57 58 /* Command line configuration */ 59 #include <config_cmd_default.h> 60 61 #define CONFIG_CMD_BOOTD 62 #define CONFIG_CMD_CACHE 63 #define CONFIG_CMD_DATE 64 #define CONFIG_CMD_DHCP 65 #define CONFIG_CMD_ELF 66 #define CONFIG_CMD_EXT2 67 #define CONFIG_CMD_FAT 68 #define CONFIG_CMD_FLASH 69 #define CONFIG_CMD_I2C 70 #define CONFIG_CMD_IDE 71 #define CONFIG_CMD_JFFS2 72 #define CONFIG_CMD_MEMORY 73 #define CONFIG_CMD_MISC 74 #define CONFIG_CMD_MII 75 #define CONFIG_CMD_NET 76 #undef CONFIG_CMD_PCI 77 #define CONFIG_CMD_PING 78 #define CONFIG_CMD_REGINFO 79 #define CONFIG_CMD_SPI 80 #define CONFIG_CMD_SF 81 82 #undef CONFIG_CMD_LOADB 83 #undef CONFIG_CMD_LOADS 84 85 /* Network configuration */ 86 #define CONFIG_MCFFEC 87 #ifdef CONFIG_MCFFEC 88 # define CONFIG_MII 1 89 # define CONFIG_MII_INIT 1 90 # define CONFIG_SYS_DISCOVER_PHY 91 # define CONFIG_SYS_RX_ETH_BUFFER 8 92 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 93 94 # define CONFIG_SYS_FEC0_PINMUX 0 95 # define CONFIG_SYS_FEC1_PINMUX 0 96 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 97 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 98 # define MCFFEC_TOUT_LOOP 50000 99 # define CONFIG_HAS_ETH1 100 101 # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 102 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" 103 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 104 # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 105 # define CONFIG_ETHPRIME "FEC0" 106 # define CONFIG_IPADDR 192.162.1.2 107 # define CONFIG_NETMASK 255.255.255.0 108 # define CONFIG_SERVERIP 192.162.1.1 109 # define CONFIG_GATEWAYIP 192.162.1.1 110 # define CONFIG_OVERWRITE_ETHADDR_ONCE 111 112 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 113 # ifndef CONFIG_SYS_DISCOVER_PHY 114 # define FECDUPLEX FULL 115 # define FECSPEED _100BASET 116 # else 117 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 118 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 119 # endif 120 # endif /* CONFIG_SYS_DISCOVER_PHY */ 121 #endif 122 123 #define CONFIG_HOSTNAME M54455EVB 124 #ifdef CONFIG_SYS_STMICRO_BOOT 125 /* ST Micro serial flash */ 126 #define CONFIG_SYS_LOAD_ADDR2 0x40010013 127 #define CONFIG_EXTRA_ENV_SETTINGS \ 128 "netdev=eth0\0" \ 129 "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 130 "loadaddr=0x40010000\0" \ 131 "sbfhdr=sbfhdr.bin\0" \ 132 "uboot=u-boot.bin\0" \ 133 "load=tftp ${loadaddr} ${sbfhdr};" \ 134 "tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 135 "upd=run load; run prog\0" \ 136 "prog=sf probe 0:1 1000000 3;" \ 137 "sf erase 0 30000;" \ 138 "sf write ${loadaddr} 0 0x30000;" \ 139 "save\0" \ 140 "" 141 #else 142 /* Atmel and Intel */ 143 #ifdef CONFIG_SYS_ATMEL_BOOT 144 # define CONFIG_SYS_UBOOT_END 0x0403FFFF 145 #elif defined(CONFIG_SYS_INTEL_BOOT) 146 # define CONFIG_SYS_UBOOT_END 0x3FFFF 147 #endif 148 #define CONFIG_EXTRA_ENV_SETTINGS \ 149 "netdev=eth0\0" \ 150 "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 151 "loadaddr=0x40010000\0" \ 152 "uboot=u-boot.bin\0" \ 153 "load=tftp ${loadaddr} ${uboot}\0" \ 154 "upd=run load; run prog\0" \ 155 "prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE) \ 156 " " MK_STR(CONFIG_SYS_UBOOT_END) ";" \ 157 "era " MK_STR(CONFIG_SYS_FLASH_BASE) " " \ 158 MK_STR(CONFIG_SYS_UBOOT_END) ";" \ 159 "cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE) \ 160 " ${filesize}; save\0" \ 161 "" 162 #endif 163 164 /* ATA configuration */ 165 #define CONFIG_ISO_PARTITION 166 #define CONFIG_DOS_PARTITION 167 #define CONFIG_IDE_RESET 1 168 #define CONFIG_IDE_PREINIT 1 169 #define CONFIG_ATAPI 170 #undef CONFIG_LBA48 171 172 #define CONFIG_SYS_IDE_MAXBUS 1 173 #define CONFIG_SYS_IDE_MAXDEVICE 2 174 175 #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 176 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 177 178 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 179 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 180 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 181 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 182 183 /* Realtime clock */ 184 #define CONFIG_MCFRTC 185 #undef RTC_DEBUG 186 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 187 188 /* Timer */ 189 #define CONFIG_MCFTMR 190 #undef CONFIG_MCFPIT 191 192 /* I2c */ 193 #define CONFIG_FSL_I2C 194 #define CONFIG_HARD_I2C /* I2C with hardware support */ 195 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 196 #define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */ 197 #define CONFIG_SYS_I2C_SLAVE 0x7F 198 #define CONFIG_SYS_I2C_OFFSET 0x58000 199 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 200 201 /* DSPI and Serial Flash */ 202 #define CONFIG_CF_SPI 203 #define CONFIG_CF_DSPI 204 #define CONFIG_HARD_SPI 205 #define CONFIG_SYS_SBFHDR_SIZE 0x13 206 #ifdef CONFIG_CMD_SPI 207 # define CONFIG_SPI_FLASH 208 # define CONFIG_SPI_FLASH_STMICRO 209 210 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 211 DSPI_CTAR_PCSSCK_1CLK | \ 212 DSPI_CTAR_PASC(0) | \ 213 DSPI_CTAR_PDT(0) | \ 214 DSPI_CTAR_CSSCK(0) | \ 215 DSPI_CTAR_ASC(0) | \ 216 DSPI_CTAR_DT(1)) 217 #endif 218 219 /* PCI */ 220 #ifdef CONFIG_CMD_PCI 221 #define CONFIG_PCI 1 222 #define CONFIG_PCI_PNP 1 223 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 224 225 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 226 227 #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 228 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 229 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 230 231 #define CONFIG_SYS_PCI_IO_BUS 0xB1000000 232 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 233 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 234 235 #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 236 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 237 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 238 #endif 239 240 /* FPGA - Spartan 2 */ 241 /* experiment 242 #define CONFIG_FPGA CONFIG_SYS_SPARTAN3 243 #define CONFIG_FPGA_COUNT 1 244 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 245 #define CONFIG_SYS_FPGA_CHECK_CTRLC 246 */ 247 248 /* Input, PCI, Flexbus, and VCO */ 249 #define CONFIG_EXTRA_CLOCK 250 251 #define CONFIG_PRAM 2048 /* 2048 KB */ 252 253 #define CONFIG_SYS_PROMPT "-> " 254 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 255 256 #if defined(CONFIG_CMD_KGDB) 257 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 258 #else 259 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 260 #endif 261 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 262 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 263 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 264 265 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 266 267 #define CONFIG_SYS_HZ 1000 268 269 #define CONFIG_SYS_MBAR 0xFC000000 270 271 /* 272 * Low Level Configuration Settings 273 * (address mappings, register initial values, etc.) 274 * You should know what you are doing if you make changes here. 275 */ 276 277 /*----------------------------------------------------------------------- 278 * Definitions for initial stack pointer and data area (in DPRAM) 279 */ 280 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 281 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 282 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 283 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 284 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 285 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 286 287 /*----------------------------------------------------------------------- 288 * Start addresses for the final memory configuration 289 * (Set up by the startup code) 290 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 291 */ 292 #define CONFIG_SYS_SDRAM_BASE 0x40000000 293 #define CONFIG_SYS_SDRAM_BASE1 0x48000000 294 #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ 295 #define CONFIG_SYS_SDRAM_CFG1 0x65311610 296 #define CONFIG_SYS_SDRAM_CFG2 0x59670000 297 #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 298 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 299 #define CONFIG_SYS_SDRAM_MODE 0x00010033 300 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA 301 302 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 303 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 304 305 #ifdef CONFIG_CF_SBF 306 # define CONFIG_SERIAL_BOOT 307 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 308 #else 309 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 310 #endif 311 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 312 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 313 314 /* Reserve 256 kB for malloc() */ 315 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 316 317 /* 318 * For booting Linux, the board info and command line data 319 * have to be in the first 8 MB of memory, since this is 320 * the maximum mapped by the Linux kernel during initialization ?? 321 */ 322 /* Initial Memory map for Linux */ 323 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 324 325 /* 326 * Configuration for environment 327 * Environment is not embedded in u-boot. First time runing may have env 328 * crc error warning if there is no correct environment on the flash. 329 */ 330 #ifdef CONFIG_CF_SBF 331 # define CONFIG_ENV_IS_IN_SPI_FLASH 332 # define CONFIG_ENV_SPI_CS 1 333 #else 334 # define CONFIG_ENV_IS_IN_FLASH 1 335 #endif 336 #undef CONFIG_ENV_OVERWRITE 337 338 /*----------------------------------------------------------------------- 339 * FLASH organization 340 */ 341 #ifdef CONFIG_SYS_STMICRO_BOOT 342 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 343 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE 344 # define CONFIG_ENV_OFFSET 0x30000 345 # define CONFIG_ENV_SIZE 0x2000 346 # define CONFIG_ENV_SECT_SIZE 0x10000 347 #endif 348 #ifdef CONFIG_SYS_ATMEL_BOOT 349 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 350 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 351 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 352 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 353 # define CONFIG_ENV_SIZE 0x2000 354 # define CONFIG_ENV_SECT_SIZE 0x10000 355 #endif 356 #ifdef CONFIG_SYS_INTEL_BOOT 357 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 358 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 359 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 360 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 361 # define CONFIG_ENV_SIZE 0x2000 362 # define CONFIG_ENV_SECT_SIZE 0x20000 363 #endif 364 365 #define CONFIG_SYS_FLASH_CFI 366 #ifdef CONFIG_SYS_FLASH_CFI 367 368 # define CONFIG_FLASH_CFI_DRIVER 1 369 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 370 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 371 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 372 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 373 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 374 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 375 # define CONFIG_SYS_FLASH_CHECKSUM 376 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 377 # define CONFIG_FLASH_CFI_LEGACY 378 379 #ifdef CONFIG_FLASH_CFI_LEGACY 380 # define CONFIG_SYS_ATMEL_REGION 4 381 # define CONFIG_SYS_ATMEL_TOTALSECT 11 382 # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} 383 # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 384 #endif 385 #endif 386 387 /* 388 * This is setting for JFFS2 support in u-boot. 389 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 390 */ 391 #ifdef CONFIG_CMD_JFFS2 392 #ifdef CF_STMICRO_BOOT 393 # define CONFIG_JFFS2_DEV "nor1" 394 # define CONFIG_JFFS2_PART_SIZE 0x01000000 395 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) 396 #endif 397 #ifdef CONFIG_SYS_ATMEL_BOOT 398 # define CONFIG_JFFS2_DEV "nor1" 399 # define CONFIG_JFFS2_PART_SIZE 0x01000000 400 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) 401 #endif 402 #ifdef CONFIG_SYS_INTEL_BOOT 403 # define CONFIG_JFFS2_DEV "nor0" 404 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 405 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 406 #endif 407 #endif 408 409 /*----------------------------------------------------------------------- 410 * Cache Configuration 411 */ 412 #define CONFIG_SYS_CACHELINE_SIZE 16 413 414 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 415 CONFIG_SYS_INIT_RAM_SIZE - 8) 416 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 417 CONFIG_SYS_INIT_RAM_SIZE - 4) 418 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 419 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 420 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 421 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 422 CF_ACR_EN | CF_ACR_SM_ALL) 423 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 424 CF_CACR_ICINVA | CF_CACR_EUSP) 425 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 426 CF_CACR_DEC | CF_CACR_DDCM_P | \ 427 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 428 429 /*----------------------------------------------------------------------- 430 * Memory bank definitions 431 */ 432 /* 433 * CS0 - NOR Flash 1, 2, 4, or 8MB 434 * CS1 - CompactFlash and registers 435 * CS2 - CPLD 436 * CS3 - FPGA 437 * CS4 - Available 438 * CS5 - Available 439 */ 440 441 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) 442 /* Atmel Flash */ 443 #define CONFIG_SYS_CS0_BASE 0x04000000 444 #define CONFIG_SYS_CS0_MASK 0x00070001 445 #define CONFIG_SYS_CS0_CTRL 0x00001140 446 /* Intel Flash */ 447 #define CONFIG_SYS_CS1_BASE 0x00000000 448 #define CONFIG_SYS_CS1_MASK 0x01FF0001 449 #define CONFIG_SYS_CS1_CTRL 0x00000D60 450 451 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE 452 #else 453 /* Intel Flash */ 454 #define CONFIG_SYS_CS0_BASE 0x00000000 455 #define CONFIG_SYS_CS0_MASK 0x01FF0001 456 #define CONFIG_SYS_CS0_CTRL 0x00000D60 457 /* Atmel Flash */ 458 #define CONFIG_SYS_CS1_BASE 0x04000000 459 #define CONFIG_SYS_CS1_MASK 0x00070001 460 #define CONFIG_SYS_CS1_CTRL 0x00001140 461 462 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE 463 #endif 464 465 /* CPLD */ 466 #define CONFIG_SYS_CS2_BASE 0x08000000 467 #define CONFIG_SYS_CS2_MASK 0x00070001 468 #define CONFIG_SYS_CS2_CTRL 0x003f1140 469 470 /* FPGA */ 471 #define CONFIG_SYS_CS3_BASE 0x09000000 472 #define CONFIG_SYS_CS3_MASK 0x00070001 473 #define CONFIG_SYS_CS3_CTRL 0x00000020 474 475 #endif /* _M54455EVB_H */ 476