1 /* 2 * Configuation settings for the Freescale MCF54455 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54455EVB_H 15 #define _M54455EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54455EVB /* M54455EVB board */ 22 23 #define CONFIG_DISPLAY_BOARDINFO 24 25 #define CONFIG_MCFUART 26 #define CONFIG_SYS_UART_PORT (0) 27 #define CONFIG_BAUDRATE 115200 28 29 #undef CONFIG_WATCHDOG 30 31 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 32 33 /* 34 * BOOTP options 35 */ 36 #define CONFIG_BOOTP_BOOTFILESIZE 37 #define CONFIG_BOOTP_BOOTPATH 38 #define CONFIG_BOOTP_GATEWAY 39 #define CONFIG_BOOTP_HOSTNAME 40 41 /* Command line configuration */ 42 #include <config_cmd_default.h> 43 44 #define CONFIG_CMD_BOOTD 45 #define CONFIG_CMD_CACHE 46 #define CONFIG_CMD_DATE 47 #define CONFIG_CMD_DHCP 48 #define CONFIG_CMD_ELF 49 #define CONFIG_CMD_EXT2 50 #define CONFIG_CMD_FAT 51 #define CONFIG_CMD_FLASH 52 #define CONFIG_CMD_I2C 53 #define CONFIG_CMD_IDE 54 #define CONFIG_CMD_JFFS2 55 #define CONFIG_CMD_MEMORY 56 #define CONFIG_CMD_MISC 57 #define CONFIG_CMD_MII 58 #define CONFIG_CMD_NET 59 #undef CONFIG_CMD_PCI 60 #define CONFIG_CMD_PING 61 #define CONFIG_CMD_REGINFO 62 #define CONFIG_CMD_SPI 63 #define CONFIG_CMD_SF 64 65 #undef CONFIG_CMD_LOADB 66 #undef CONFIG_CMD_LOADS 67 68 /* Network configuration */ 69 #define CONFIG_MCFFEC 70 #ifdef CONFIG_MCFFEC 71 # define CONFIG_MII 1 72 # define CONFIG_MII_INIT 1 73 # define CONFIG_SYS_DISCOVER_PHY 74 # define CONFIG_SYS_RX_ETH_BUFFER 8 75 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 76 77 # define CONFIG_SYS_FEC0_PINMUX 0 78 # define CONFIG_SYS_FEC1_PINMUX 0 79 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 80 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 81 # define MCFFEC_TOUT_LOOP 50000 82 # define CONFIG_HAS_ETH1 83 84 # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 85 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" 86 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 87 # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 88 # define CONFIG_ETHPRIME "FEC0" 89 # define CONFIG_IPADDR 192.162.1.2 90 # define CONFIG_NETMASK 255.255.255.0 91 # define CONFIG_SERVERIP 192.162.1.1 92 # define CONFIG_GATEWAYIP 192.162.1.1 93 # define CONFIG_OVERWRITE_ETHADDR_ONCE 94 95 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 96 # ifndef CONFIG_SYS_DISCOVER_PHY 97 # define FECDUPLEX FULL 98 # define FECSPEED _100BASET 99 # else 100 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 101 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 102 # endif 103 # endif /* CONFIG_SYS_DISCOVER_PHY */ 104 #endif 105 106 #define CONFIG_HOSTNAME M54455EVB 107 #ifdef CONFIG_SYS_STMICRO_BOOT 108 /* ST Micro serial flash */ 109 #define CONFIG_SYS_LOAD_ADDR2 0x40010013 110 #define CONFIG_EXTRA_ENV_SETTINGS \ 111 "netdev=eth0\0" \ 112 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 113 "loadaddr=0x40010000\0" \ 114 "sbfhdr=sbfhdr.bin\0" \ 115 "uboot=u-boot.bin\0" \ 116 "load=tftp ${loadaddr} ${sbfhdr};" \ 117 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 118 "upd=run load; run prog\0" \ 119 "prog=sf probe 0:1 1000000 3;" \ 120 "sf erase 0 30000;" \ 121 "sf write ${loadaddr} 0 0x30000;" \ 122 "save\0" \ 123 "" 124 #else 125 /* Atmel and Intel */ 126 #ifdef CONFIG_SYS_ATMEL_BOOT 127 # define CONFIG_SYS_UBOOT_END 0x0403FFFF 128 #elif defined(CONFIG_SYS_INTEL_BOOT) 129 # define CONFIG_SYS_UBOOT_END 0x3FFFF 130 #endif 131 #define CONFIG_EXTRA_ENV_SETTINGS \ 132 "netdev=eth0\0" \ 133 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 134 "loadaddr=0x40010000\0" \ 135 "uboot=u-boot.bin\0" \ 136 "load=tftp ${loadaddr} ${uboot}\0" \ 137 "upd=run load; run prog\0" \ 138 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 139 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 140 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 141 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 142 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 143 " ${filesize}; save\0" \ 144 "" 145 #endif 146 147 /* ATA configuration */ 148 #define CONFIG_ISO_PARTITION 149 #define CONFIG_DOS_PARTITION 150 #define CONFIG_IDE_RESET 1 151 #define CONFIG_IDE_PREINIT 1 152 #define CONFIG_ATAPI 153 #undef CONFIG_LBA48 154 155 #define CONFIG_SYS_IDE_MAXBUS 1 156 #define CONFIG_SYS_IDE_MAXDEVICE 2 157 158 #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 159 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 160 161 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 162 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 163 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 164 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 165 166 /* Realtime clock */ 167 #define CONFIG_MCFRTC 168 #undef RTC_DEBUG 169 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 170 171 /* Timer */ 172 #define CONFIG_MCFTMR 173 #undef CONFIG_MCFPIT 174 175 /* I2c */ 176 #define CONFIG_SYS_I2C 177 #define CONFIG_SYS_I2C_FSL 178 #define CONFIG_SYS_FSL_I2C_SPEED 80000 179 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 180 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 181 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 182 183 /* DSPI and Serial Flash */ 184 #define CONFIG_CF_SPI 185 #define CONFIG_CF_DSPI 186 #define CONFIG_HARD_SPI 187 #define CONFIG_SYS_SBFHDR_SIZE 0x13 188 #ifdef CONFIG_CMD_SPI 189 # define CONFIG_SPI_FLASH 190 # define CONFIG_SPI_FLASH_STMICRO 191 192 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 193 DSPI_CTAR_PCSSCK_1CLK | \ 194 DSPI_CTAR_PASC(0) | \ 195 DSPI_CTAR_PDT(0) | \ 196 DSPI_CTAR_CSSCK(0) | \ 197 DSPI_CTAR_ASC(0) | \ 198 DSPI_CTAR_DT(1)) 199 #endif 200 201 /* PCI */ 202 #ifdef CONFIG_CMD_PCI 203 #define CONFIG_PCI 1 204 #define CONFIG_PCI_PNP 1 205 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 206 207 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 208 209 #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 210 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 211 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 212 213 #define CONFIG_SYS_PCI_IO_BUS 0xB1000000 214 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 215 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 216 217 #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 218 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 219 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 220 #endif 221 222 /* FPGA - Spartan 2 */ 223 /* experiment 224 #define CONFIG_FPGA 225 #define CONFIG_FPGA_COUNT 1 226 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 227 #define CONFIG_SYS_FPGA_CHECK_CTRLC 228 */ 229 230 /* Input, PCI, Flexbus, and VCO */ 231 #define CONFIG_EXTRA_CLOCK 232 233 #define CONFIG_PRAM 2048 /* 2048 KB */ 234 235 #define CONFIG_SYS_PROMPT "-> " 236 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 237 238 #if defined(CONFIG_CMD_KGDB) 239 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 240 #else 241 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 242 #endif 243 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 244 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 245 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 246 247 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 248 249 #define CONFIG_SYS_MBAR 0xFC000000 250 251 /* 252 * Low Level Configuration Settings 253 * (address mappings, register initial values, etc.) 254 * You should know what you are doing if you make changes here. 255 */ 256 257 /*----------------------------------------------------------------------- 258 * Definitions for initial stack pointer and data area (in DPRAM) 259 */ 260 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 261 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 262 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 263 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 264 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 265 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 266 267 /*----------------------------------------------------------------------- 268 * Start addresses for the final memory configuration 269 * (Set up by the startup code) 270 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 271 */ 272 #define CONFIG_SYS_SDRAM_BASE 0x40000000 273 #define CONFIG_SYS_SDRAM_BASE1 0x48000000 274 #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ 275 #define CONFIG_SYS_SDRAM_CFG1 0x65311610 276 #define CONFIG_SYS_SDRAM_CFG2 0x59670000 277 #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 278 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 279 #define CONFIG_SYS_SDRAM_MODE 0x00010033 280 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA 281 282 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 283 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 284 285 #ifdef CONFIG_CF_SBF 286 # define CONFIG_SERIAL_BOOT 287 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 288 #else 289 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 290 #endif 291 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 292 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 293 294 /* Reserve 256 kB for malloc() */ 295 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 296 297 /* 298 * For booting Linux, the board info and command line data 299 * have to be in the first 8 MB of memory, since this is 300 * the maximum mapped by the Linux kernel during initialization ?? 301 */ 302 /* Initial Memory map for Linux */ 303 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 304 305 /* 306 * Configuration for environment 307 * Environment is not embedded in u-boot. First time runing may have env 308 * crc error warning if there is no correct environment on the flash. 309 */ 310 #ifdef CONFIG_CF_SBF 311 # define CONFIG_ENV_IS_IN_SPI_FLASH 312 # define CONFIG_ENV_SPI_CS 1 313 #else 314 # define CONFIG_ENV_IS_IN_FLASH 1 315 #endif 316 #undef CONFIG_ENV_OVERWRITE 317 318 /*----------------------------------------------------------------------- 319 * FLASH organization 320 */ 321 #ifdef CONFIG_SYS_STMICRO_BOOT 322 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 323 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE 324 # define CONFIG_ENV_OFFSET 0x30000 325 # define CONFIG_ENV_SIZE 0x2000 326 # define CONFIG_ENV_SECT_SIZE 0x10000 327 #endif 328 #ifdef CONFIG_SYS_ATMEL_BOOT 329 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 330 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 331 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 332 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 333 # define CONFIG_ENV_SIZE 0x2000 334 # define CONFIG_ENV_SECT_SIZE 0x10000 335 #endif 336 #ifdef CONFIG_SYS_INTEL_BOOT 337 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 338 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 339 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 340 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 341 # define CONFIG_ENV_SIZE 0x2000 342 # define CONFIG_ENV_SECT_SIZE 0x20000 343 #endif 344 345 #define CONFIG_SYS_FLASH_CFI 346 #ifdef CONFIG_SYS_FLASH_CFI 347 348 # define CONFIG_FLASH_CFI_DRIVER 1 349 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 350 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 351 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 352 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 353 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 354 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 355 # define CONFIG_SYS_FLASH_CHECKSUM 356 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 357 # define CONFIG_FLASH_CFI_LEGACY 358 359 #ifdef CONFIG_FLASH_CFI_LEGACY 360 # define CONFIG_SYS_ATMEL_REGION 4 361 # define CONFIG_SYS_ATMEL_TOTALSECT 11 362 # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} 363 # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 364 #endif 365 #endif 366 367 /* 368 * This is setting for JFFS2 support in u-boot. 369 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 370 */ 371 #ifdef CONFIG_CMD_JFFS2 372 #ifdef CF_STMICRO_BOOT 373 # define CONFIG_JFFS2_DEV "nor1" 374 # define CONFIG_JFFS2_PART_SIZE 0x01000000 375 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) 376 #endif 377 #ifdef CONFIG_SYS_ATMEL_BOOT 378 # define CONFIG_JFFS2_DEV "nor1" 379 # define CONFIG_JFFS2_PART_SIZE 0x01000000 380 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) 381 #endif 382 #ifdef CONFIG_SYS_INTEL_BOOT 383 # define CONFIG_JFFS2_DEV "nor0" 384 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 385 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 386 #endif 387 #endif 388 389 /*----------------------------------------------------------------------- 390 * Cache Configuration 391 */ 392 #define CONFIG_SYS_CACHELINE_SIZE 16 393 394 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 395 CONFIG_SYS_INIT_RAM_SIZE - 8) 396 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 397 CONFIG_SYS_INIT_RAM_SIZE - 4) 398 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 399 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 400 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 401 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 402 CF_ACR_EN | CF_ACR_SM_ALL) 403 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 404 CF_CACR_ICINVA | CF_CACR_EUSP) 405 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 406 CF_CACR_DEC | CF_CACR_DDCM_P | \ 407 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 408 409 /*----------------------------------------------------------------------- 410 * Memory bank definitions 411 */ 412 /* 413 * CS0 - NOR Flash 1, 2, 4, or 8MB 414 * CS1 - CompactFlash and registers 415 * CS2 - CPLD 416 * CS3 - FPGA 417 * CS4 - Available 418 * CS5 - Available 419 */ 420 421 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) 422 /* Atmel Flash */ 423 #define CONFIG_SYS_CS0_BASE 0x04000000 424 #define CONFIG_SYS_CS0_MASK 0x00070001 425 #define CONFIG_SYS_CS0_CTRL 0x00001140 426 /* Intel Flash */ 427 #define CONFIG_SYS_CS1_BASE 0x00000000 428 #define CONFIG_SYS_CS1_MASK 0x01FF0001 429 #define CONFIG_SYS_CS1_CTRL 0x00000D60 430 431 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE 432 #else 433 /* Intel Flash */ 434 #define CONFIG_SYS_CS0_BASE 0x00000000 435 #define CONFIG_SYS_CS0_MASK 0x01FF0001 436 #define CONFIG_SYS_CS0_CTRL 0x00000D60 437 /* Atmel Flash */ 438 #define CONFIG_SYS_CS1_BASE 0x04000000 439 #define CONFIG_SYS_CS1_MASK 0x00070001 440 #define CONFIG_SYS_CS1_CTRL 0x00001140 441 442 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE 443 #endif 444 445 /* CPLD */ 446 #define CONFIG_SYS_CS2_BASE 0x08000000 447 #define CONFIG_SYS_CS2_MASK 0x00070001 448 #define CONFIG_SYS_CS2_CTRL 0x003f1140 449 450 /* FPGA */ 451 #define CONFIG_SYS_CS3_BASE 0x09000000 452 #define CONFIG_SYS_CS3_MASK 0x00070001 453 #define CONFIG_SYS_CS3_CTRL 0x00000020 454 455 #endif /* _M54455EVB_H */ 456