1 /* 2 * Configuation settings for the Freescale MCF54455 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef _M54455EVB_H 31 #define _M54455EVB_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_MCF5445x /* define processor family */ 38 #define CONFIG_M54455 /* define processor type */ 39 #define CONFIG_M54455EVB /* M54455EVB board */ 40 41 #define CONFIG_MCFUART 42 #define CONFIG_SYS_UART_PORT (0) 43 #define CONFIG_BAUDRATE 115200 44 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 45 46 #undef CONFIG_WATCHDOG 47 48 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 49 50 /* 51 * BOOTP options 52 */ 53 #define CONFIG_BOOTP_BOOTFILESIZE 54 #define CONFIG_BOOTP_BOOTPATH 55 #define CONFIG_BOOTP_GATEWAY 56 #define CONFIG_BOOTP_HOSTNAME 57 58 /* Command line configuration */ 59 #include <config_cmd_default.h> 60 61 #define CONFIG_CMD_BOOTD 62 #define CONFIG_CMD_CACHE 63 #define CONFIG_CMD_DATE 64 #define CONFIG_CMD_DHCP 65 #define CONFIG_CMD_ELF 66 #define CONFIG_CMD_EXT2 67 #define CONFIG_CMD_FAT 68 #define CONFIG_CMD_FLASH 69 #define CONFIG_CMD_I2C 70 #define CONFIG_CMD_IDE 71 #define CONFIG_CMD_JFFS2 72 #define CONFIG_CMD_MEMORY 73 #define CONFIG_CMD_MISC 74 #define CONFIG_CMD_MII 75 #define CONFIG_CMD_NET 76 #undef CONFIG_CMD_PCI 77 #define CONFIG_CMD_PING 78 #define CONFIG_CMD_REGINFO 79 #define CONFIG_CMD_SPI 80 #define CONFIG_CMD_SF 81 82 #undef CONFIG_CMD_LOADB 83 #undef CONFIG_CMD_LOADS 84 85 /* Network configuration */ 86 #define CONFIG_MCFFEC 87 #ifdef CONFIG_MCFFEC 88 # define CONFIG_NET_MULTI 1 89 # define CONFIG_MII 1 90 # define CONFIG_MII_INIT 1 91 # define CONFIG_SYS_DISCOVER_PHY 92 # define CONFIG_SYS_RX_ETH_BUFFER 8 93 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 94 95 # define CONFIG_SYS_FEC0_PINMUX 0 96 # define CONFIG_SYS_FEC1_PINMUX 0 97 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 98 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 99 # define MCFFEC_TOUT_LOOP 50000 100 # define CONFIG_HAS_ETH1 101 102 # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 103 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" 104 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 105 # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 106 # define CONFIG_ETHPRIME "FEC0" 107 # define CONFIG_IPADDR 192.162.1.2 108 # define CONFIG_NETMASK 255.255.255.0 109 # define CONFIG_SERVERIP 192.162.1.1 110 # define CONFIG_GATEWAYIP 192.162.1.1 111 # define CONFIG_OVERWRITE_ETHADDR_ONCE 112 113 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 114 # ifndef CONFIG_SYS_DISCOVER_PHY 115 # define FECDUPLEX FULL 116 # define FECSPEED _100BASET 117 # else 118 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 119 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 120 # endif 121 # endif /* CONFIG_SYS_DISCOVER_PHY */ 122 #endif 123 124 #define CONFIG_HOSTNAME M54455EVB 125 #ifdef CONFIG_SYS_STMICRO_BOOT 126 /* ST Micro serial flash */ 127 #define CONFIG_SYS_LOAD_ADDR2 0x40010013 128 #define CONFIG_EXTRA_ENV_SETTINGS \ 129 "netdev=eth0\0" \ 130 "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 131 "loadaddr=0x40010000\0" \ 132 "sbfhdr=sbfhdr.bin\0" \ 133 "uboot=u-boot.bin\0" \ 134 "load=tftp ${loadaddr} ${sbfhdr};" \ 135 "tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 136 "upd=run load; run prog\0" \ 137 "prog=sf probe 0:1 10000 1;" \ 138 "sf erase 0 30000;" \ 139 "sf write ${loadaddr} 0 0x30000;" \ 140 "save\0" \ 141 "" 142 #else 143 /* Atmel and Intel */ 144 #ifdef CONFIG_SYS_ATMEL_BOOT 145 # define CONFIG_SYS_UBOOT_END 0x0403FFFF 146 #elif defined(CONFIG_SYS_INTEL_BOOT) 147 # define CONFIG_SYS_UBOOT_END 0x3FFFF 148 #endif 149 #define CONFIG_EXTRA_ENV_SETTINGS \ 150 "netdev=eth0\0" \ 151 "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 152 "loadaddr=0x40010000\0" \ 153 "uboot=u-boot.bin\0" \ 154 "load=tftp ${loadaddr} ${uboot}\0" \ 155 "upd=run load; run prog\0" \ 156 "prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE) \ 157 " " MK_STR(CONFIG_SYS_UBOOT_END) ";" \ 158 "era " MK_STR(CONFIG_SYS_FLASH_BASE) " " \ 159 MK_STR(CONFIG_SYS_UBOOT_END) ";" \ 160 "cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE) \ 161 " ${filesize}; save\0" \ 162 "" 163 #endif 164 165 /* ATA configuration */ 166 #define CONFIG_ISO_PARTITION 167 #define CONFIG_DOS_PARTITION 168 #define CONFIG_IDE_RESET 1 169 #define CONFIG_IDE_PREINIT 1 170 #define CONFIG_ATAPI 171 #undef CONFIG_LBA48 172 173 #define CONFIG_SYS_IDE_MAXBUS 1 174 #define CONFIG_SYS_IDE_MAXDEVICE 2 175 176 #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 177 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 178 179 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 180 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 181 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 182 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 183 184 /* Realtime clock */ 185 #define CONFIG_MCFRTC 186 #undef RTC_DEBUG 187 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 188 189 /* Timer */ 190 #define CONFIG_MCFTMR 191 #undef CONFIG_MCFPIT 192 193 /* I2c */ 194 #define CONFIG_FSL_I2C 195 #define CONFIG_HARD_I2C /* I2C with hardware support */ 196 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 197 #define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */ 198 #define CONFIG_SYS_I2C_SLAVE 0x7F 199 #define CONFIG_SYS_I2C_OFFSET 0x58000 200 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 201 202 /* DSPI and Serial Flash */ 203 #define CONFIG_CF_SPI 204 #define CONFIG_CF_DSPI 205 #define CONFIG_HARD_SPI 206 #define CONFIG_SYS_SBFHDR_SIZE 0x13 207 #ifdef CONFIG_CMD_SPI 208 # define CONFIG_SPI_FLASH 209 # define CONFIG_SPI_FLASH_STMICRO 210 211 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 212 DSPI_CTAR_PCSSCK_1CLK | \ 213 DSPI_CTAR_PASC(0) | \ 214 DSPI_CTAR_PDT(0) | \ 215 DSPI_CTAR_CSSCK(0) | \ 216 DSPI_CTAR_ASC(0) | \ 217 DSPI_CTAR_DT(1)) 218 #endif 219 220 /* PCI */ 221 #ifdef CONFIG_CMD_PCI 222 #define CONFIG_PCI 1 223 #define CONFIG_PCI_PNP 1 224 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 225 226 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 227 228 #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 229 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 230 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 231 232 #define CONFIG_SYS_PCI_IO_BUS 0xB1000000 233 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 234 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 235 236 #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 237 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 238 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 239 #endif 240 241 /* FPGA - Spartan 2 */ 242 /* experiment 243 #define CONFIG_FPGA CONFIG_SYS_SPARTAN3 244 #define CONFIG_FPGA_COUNT 1 245 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 246 #define CONFIG_SYS_FPGA_CHECK_CTRLC 247 */ 248 249 /* Input, PCI, Flexbus, and VCO */ 250 #define CONFIG_EXTRA_CLOCK 251 252 #define CONFIG_PRAM 2048 /* 2048 KB */ 253 254 #define CONFIG_SYS_PROMPT "-> " 255 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 256 257 #if defined(CONFIG_CMD_KGDB) 258 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 259 #else 260 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 261 #endif 262 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 263 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 264 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 265 266 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 267 268 #define CONFIG_SYS_HZ 1000 269 270 #define CONFIG_SYS_MBAR 0xFC000000 271 272 /* 273 * Low Level Configuration Settings 274 * (address mappings, register initial values, etc.) 275 * You should know what you are doing if you make changes here. 276 */ 277 278 /*----------------------------------------------------------------------- 279 * Definitions for initial stack pointer and data area (in DPRAM) 280 */ 281 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 282 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 283 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 284 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 285 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 286 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 287 288 /*----------------------------------------------------------------------- 289 * Start addresses for the final memory configuration 290 * (Set up by the startup code) 291 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 292 */ 293 #define CONFIG_SYS_SDRAM_BASE 0x40000000 294 #define CONFIG_SYS_SDRAM_BASE1 0x48000000 295 #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ 296 #define CONFIG_SYS_SDRAM_CFG1 0x65311610 297 #define CONFIG_SYS_SDRAM_CFG2 0x59670000 298 #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 299 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 300 #define CONFIG_SYS_SDRAM_MODE 0x00010033 301 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA 302 303 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 304 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 305 306 #ifdef CONFIG_CF_SBF 307 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 308 #else 309 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 310 #endif 311 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 312 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 313 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 314 315 /* 316 * For booting Linux, the board info and command line data 317 * have to be in the first 8 MB of memory, since this is 318 * the maximum mapped by the Linux kernel during initialization ?? 319 */ 320 /* Initial Memory map for Linux */ 321 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 322 323 /* 324 * Configuration for environment 325 * Environment is embedded in u-boot in the second sector of the flash 326 */ 327 #ifdef CONFIG_CF_SBF 328 # define CONFIG_ENV_IS_IN_SPI_FLASH 329 # define CONFIG_ENV_SPI_CS 1 330 #else 331 # define CONFIG_ENV_IS_IN_FLASH 1 332 #endif 333 #undef CONFIG_ENV_OVERWRITE 334 335 /*----------------------------------------------------------------------- 336 * FLASH organization 337 */ 338 #ifdef CONFIG_SYS_STMICRO_BOOT 339 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 340 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE 341 # define CONFIG_ENV_OFFSET 0x30000 342 # define CONFIG_ENV_SIZE 0x2000 343 # define CONFIG_ENV_SECT_SIZE 0x10000 344 #endif 345 #ifdef CONFIG_SYS_ATMEL_BOOT 346 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 347 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 348 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 349 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) 350 # define CONFIG_ENV_SECT_SIZE 0x2000 351 #endif 352 #ifdef CONFIG_SYS_INTEL_BOOT 353 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 354 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 355 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 356 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 357 # define CONFIG_ENV_SIZE 0x2000 358 # define CONFIG_ENV_SECT_SIZE 0x20000 359 #endif 360 361 #define CONFIG_SYS_FLASH_CFI 362 #ifdef CONFIG_SYS_FLASH_CFI 363 364 # define CONFIG_FLASH_CFI_DRIVER 1 365 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 366 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 367 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 368 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 369 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 370 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 371 # define CONFIG_SYS_FLASH_CHECKSUM 372 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 373 # define CONFIG_FLASH_CFI_LEGACY 374 375 #ifdef CONFIG_FLASH_CFI_LEGACY 376 # define CONFIG_SYS_ATMEL_REGION 4 377 # define CONFIG_SYS_ATMEL_TOTALSECT 11 378 # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} 379 # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 380 #endif 381 #endif 382 383 /* 384 * This is setting for JFFS2 support in u-boot. 385 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 386 */ 387 #ifdef CONFIG_CMD_JFFS2 388 #ifdef CF_STMICRO_BOOT 389 # define CONFIG_JFFS2_DEV "nor1" 390 # define CONFIG_JFFS2_PART_SIZE 0x01000000 391 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) 392 #endif 393 #ifdef CONFIG_SYS_ATMEL_BOOT 394 # define CONFIG_JFFS2_DEV "nor1" 395 # define CONFIG_JFFS2_PART_SIZE 0x01000000 396 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) 397 #endif 398 #ifdef CONFIG_SYS_INTEL_BOOT 399 # define CONFIG_JFFS2_DEV "nor0" 400 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 401 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 402 #endif 403 #endif 404 405 /*----------------------------------------------------------------------- 406 * Cache Configuration 407 */ 408 #define CONFIG_SYS_CACHELINE_SIZE 16 409 410 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 411 CONFIG_SYS_INIT_RAM_SIZE - 8) 412 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 413 CONFIG_SYS_INIT_RAM_SIZE - 4) 414 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 415 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 416 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 417 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 418 CF_ACR_EN | CF_ACR_SM_ALL) 419 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 420 CF_CACR_ICINVA | CF_CACR_EUSP) 421 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 422 CF_CACR_DEC | CF_CACR_DDCM_P | \ 423 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 424 425 /*----------------------------------------------------------------------- 426 * Memory bank definitions 427 */ 428 /* 429 * CS0 - NOR Flash 1, 2, 4, or 8MB 430 * CS1 - CompactFlash and registers 431 * CS2 - CPLD 432 * CS3 - FPGA 433 * CS4 - Available 434 * CS5 - Available 435 */ 436 437 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) 438 /* Atmel Flash */ 439 #define CONFIG_SYS_CS0_BASE 0x04000000 440 #define CONFIG_SYS_CS0_MASK 0x00070001 441 #define CONFIG_SYS_CS0_CTRL 0x00001140 442 /* Intel Flash */ 443 #define CONFIG_SYS_CS1_BASE 0x00000000 444 #define CONFIG_SYS_CS1_MASK 0x01FF0001 445 #define CONFIG_SYS_CS1_CTRL 0x00000D60 446 447 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE 448 #else 449 /* Intel Flash */ 450 #define CONFIG_SYS_CS0_BASE 0x00000000 451 #define CONFIG_SYS_CS0_MASK 0x01FF0001 452 #define CONFIG_SYS_CS0_CTRL 0x00000D60 453 /* Atmel Flash */ 454 #define CONFIG_SYS_CS1_BASE 0x04000000 455 #define CONFIG_SYS_CS1_MASK 0x00070001 456 #define CONFIG_SYS_CS1_CTRL 0x00001140 457 458 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE 459 #endif 460 461 /* CPLD */ 462 #define CONFIG_SYS_CS2_BASE 0x08000000 463 #define CONFIG_SYS_CS2_MASK 0x00070001 464 #define CONFIG_SYS_CS2_CTRL 0x003f1140 465 466 /* FPGA */ 467 #define CONFIG_SYS_CS3_BASE 0x09000000 468 #define CONFIG_SYS_CS3_MASK 0x00070001 469 #define CONFIG_SYS_CS3_CTRL 0x00000020 470 471 #endif /* _M54455EVB_H */ 472