1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Freescale MCF54455 EVB board. 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M54455EVB_H 14 #define _M54455EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 #define CONFIG_M54455EVB /* M54455EVB board */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #define LDS_BOARD_TEXT board/freescale/m54455evb/sbf_dram_init.o (.text*) 26 27 #undef CONFIG_WATCHDOG 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 36 /* Network configuration */ 37 #define CONFIG_MCFFEC 38 #ifdef CONFIG_MCFFEC 39 # define CONFIG_MII_INIT 1 40 # define CONFIG_SYS_DISCOVER_PHY 41 # define CONFIG_SYS_RX_ETH_BUFFER 8 42 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 43 44 # define CONFIG_SYS_FEC0_PINMUX 0 45 # define CONFIG_SYS_FEC1_PINMUX 0 46 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 47 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 48 # define MCFFEC_TOUT_LOOP 50000 49 # define CONFIG_HAS_ETH1 50 51 # define CONFIG_ETHPRIME "FEC0" 52 # define CONFIG_IPADDR 192.162.1.2 53 # define CONFIG_NETMASK 255.255.255.0 54 # define CONFIG_SERVERIP 192.162.1.1 55 # define CONFIG_GATEWAYIP 192.162.1.1 56 57 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 58 # ifndef CONFIG_SYS_DISCOVER_PHY 59 # define FECDUPLEX FULL 60 # define FECSPEED _100BASET 61 # else 62 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 63 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 64 # endif 65 # endif /* CONFIG_SYS_DISCOVER_PHY */ 66 #endif 67 68 #define CONFIG_HOSTNAME "M54455EVB" 69 #ifdef CONFIG_SYS_STMICRO_BOOT 70 /* ST Micro serial flash */ 71 #define CONFIG_SYS_LOAD_ADDR2 0x40010013 72 #define CONFIG_EXTRA_ENV_SETTINGS \ 73 "netdev=eth0\0" \ 74 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 75 "loadaddr=0x40010000\0" \ 76 "sbfhdr=sbfhdr.bin\0" \ 77 "uboot=u-boot.bin\0" \ 78 "load=tftp ${loadaddr} ${sbfhdr};" \ 79 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 80 "upd=run load; run prog\0" \ 81 "prog=sf probe 0:1 1000000 3;" \ 82 "sf erase 0 30000;" \ 83 "sf write ${loadaddr} 0 0x30000;" \ 84 "save\0" \ 85 "" 86 #else 87 /* Atmel and Intel */ 88 #ifdef CONFIG_SYS_ATMEL_BOOT 89 # define CONFIG_SYS_UBOOT_END 0x0403FFFF 90 #elif defined(CONFIG_SYS_INTEL_BOOT) 91 # define CONFIG_SYS_UBOOT_END 0x3FFFF 92 #endif 93 #define CONFIG_EXTRA_ENV_SETTINGS \ 94 "netdev=eth0\0" \ 95 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 96 "loadaddr=0x40010000\0" \ 97 "uboot=u-boot.bin\0" \ 98 "load=tftp ${loadaddr} ${uboot}\0" \ 99 "upd=run load; run prog\0" \ 100 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 101 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 102 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 103 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 104 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 105 " ${filesize}; save\0" \ 106 "" 107 #endif 108 109 /* ATA configuration */ 110 #define CONFIG_IDE_RESET 1 111 #define CONFIG_IDE_PREINIT 1 112 #define CONFIG_ATAPI 113 #undef CONFIG_LBA48 114 115 #define CONFIG_SYS_IDE_MAXBUS 1 116 #define CONFIG_SYS_IDE_MAXDEVICE 2 117 118 #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 119 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 120 121 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 122 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 123 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 124 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 125 126 /* Realtime clock */ 127 #define CONFIG_MCFRTC 128 #undef RTC_DEBUG 129 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 130 131 /* Timer */ 132 #define CONFIG_MCFTMR 133 #undef CONFIG_MCFPIT 134 135 /* I2c */ 136 #define CONFIG_SYS_I2C 137 #define CONFIG_SYS_I2C_FSL 138 #define CONFIG_SYS_FSL_I2C_SPEED 80000 139 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 140 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 141 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 142 143 /* DSPI and Serial Flash */ 144 #define CONFIG_CF_DSPI 145 #define CONFIG_HARD_SPI 146 #define CONFIG_SYS_SBFHDR_SIZE 0x13 147 #ifdef CONFIG_CMD_SPI 148 149 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 150 DSPI_CTAR_PCSSCK_1CLK | \ 151 DSPI_CTAR_PASC(0) | \ 152 DSPI_CTAR_PDT(0) | \ 153 DSPI_CTAR_CSSCK(0) | \ 154 DSPI_CTAR_ASC(0) | \ 155 DSPI_CTAR_DT(1)) 156 #endif 157 158 /* PCI */ 159 #ifdef CONFIG_CMD_PCI 160 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 161 162 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 163 164 #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 165 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 166 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 167 168 #define CONFIG_SYS_PCI_IO_BUS 0xB1000000 169 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 170 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 171 172 #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 173 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 174 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 175 #endif 176 177 /* FPGA - Spartan 2 */ 178 /* experiment 179 #define CONFIG_FPGA_COUNT 1 180 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 181 #define CONFIG_SYS_FPGA_CHECK_CTRLC 182 */ 183 184 /* Input, PCI, Flexbus, and VCO */ 185 #define CONFIG_EXTRA_CLOCK 186 187 #define CONFIG_PRAM 2048 /* 2048 KB */ 188 189 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 190 191 #define CONFIG_SYS_MBAR 0xFC000000 192 193 /* 194 * Low Level Configuration Settings 195 * (address mappings, register initial values, etc.) 196 * You should know what you are doing if you make changes here. 197 */ 198 199 /*----------------------------------------------------------------------- 200 * Definitions for initial stack pointer and data area (in DPRAM) 201 */ 202 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 203 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 204 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 205 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 206 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 207 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 208 209 /*----------------------------------------------------------------------- 210 * Start addresses for the final memory configuration 211 * (Set up by the startup code) 212 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 213 */ 214 #define CONFIG_SYS_SDRAM_BASE 0x40000000 215 #define CONFIG_SYS_SDRAM_BASE1 0x48000000 216 #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ 217 #define CONFIG_SYS_SDRAM_CFG1 0x65311610 218 #define CONFIG_SYS_SDRAM_CFG2 0x59670000 219 #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 220 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 221 #define CONFIG_SYS_SDRAM_MODE 0x00010033 222 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA 223 224 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 225 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 226 227 #ifdef CONFIG_CF_SBF 228 # define CONFIG_SERIAL_BOOT 229 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 230 #else 231 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 232 #endif 233 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 234 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 235 236 /* Reserve 256 kB for malloc() */ 237 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 238 239 /* 240 * For booting Linux, the board info and command line data 241 * have to be in the first 8 MB of memory, since this is 242 * the maximum mapped by the Linux kernel during initialization ?? 243 */ 244 /* Initial Memory map for Linux */ 245 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 246 247 /* 248 * Configuration for environment 249 * Environment is not embedded in u-boot. First time runing may have env 250 * crc error warning if there is no correct environment on the flash. 251 */ 252 #ifdef CONFIG_CF_SBF 253 # define CONFIG_ENV_SPI_CS 1 254 #endif 255 #undef CONFIG_ENV_OVERWRITE 256 257 /*----------------------------------------------------------------------- 258 * FLASH organization 259 */ 260 #ifdef CONFIG_SYS_STMICRO_BOOT 261 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 262 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE 263 # define CONFIG_ENV_OFFSET 0x30000 264 # define CONFIG_ENV_SIZE 0x2000 265 # define CONFIG_ENV_SECT_SIZE 0x10000 266 #endif 267 #ifdef CONFIG_SYS_ATMEL_BOOT 268 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 269 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 270 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 271 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 272 # define CONFIG_ENV_SIZE 0x2000 273 # define CONFIG_ENV_SECT_SIZE 0x10000 274 #endif 275 #ifdef CONFIG_SYS_INTEL_BOOT 276 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 277 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 278 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 279 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 280 # define CONFIG_ENV_SIZE 0x2000 281 # define CONFIG_ENV_SECT_SIZE 0x20000 282 #endif 283 284 #ifdef CONFIG_SYS_FLASH_CFI 285 286 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 287 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 288 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 289 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 290 # define CONFIG_SYS_FLASH_CHECKSUM 291 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 292 # define CONFIG_FLASH_CFI_LEGACY 293 294 #ifdef CONFIG_FLASH_CFI_LEGACY 295 # define CONFIG_SYS_ATMEL_REGION 4 296 # define CONFIG_SYS_ATMEL_TOTALSECT 11 297 # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} 298 # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 299 #endif 300 #endif 301 302 /* 303 * This is setting for JFFS2 support in u-boot. 304 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 305 */ 306 #ifdef CONFIG_CMD_JFFS2 307 #ifdef CF_STMICRO_BOOT 308 # define CONFIG_JFFS2_DEV "nor1" 309 # define CONFIG_JFFS2_PART_SIZE 0x01000000 310 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) 311 #endif 312 #ifdef CONFIG_SYS_ATMEL_BOOT 313 # define CONFIG_JFFS2_DEV "nor1" 314 # define CONFIG_JFFS2_PART_SIZE 0x01000000 315 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) 316 #endif 317 #ifdef CONFIG_SYS_INTEL_BOOT 318 # define CONFIG_JFFS2_DEV "nor0" 319 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 320 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 321 #endif 322 #endif 323 324 /*----------------------------------------------------------------------- 325 * Cache Configuration 326 */ 327 #define CONFIG_SYS_CACHELINE_SIZE 16 328 329 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 330 CONFIG_SYS_INIT_RAM_SIZE - 8) 331 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 332 CONFIG_SYS_INIT_RAM_SIZE - 4) 333 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 334 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 335 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 336 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 337 CF_ACR_EN | CF_ACR_SM_ALL) 338 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 339 CF_CACR_ICINVA | CF_CACR_EUSP) 340 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 341 CF_CACR_DEC | CF_CACR_DDCM_P | \ 342 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 343 344 /*----------------------------------------------------------------------- 345 * Memory bank definitions 346 */ 347 /* 348 * CS0 - NOR Flash 1, 2, 4, or 8MB 349 * CS1 - CompactFlash and registers 350 * CS2 - CPLD 351 * CS3 - FPGA 352 * CS4 - Available 353 * CS5 - Available 354 */ 355 356 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) 357 /* Atmel Flash */ 358 #define CONFIG_SYS_CS0_BASE 0x04000000 359 #define CONFIG_SYS_CS0_MASK 0x00070001 360 #define CONFIG_SYS_CS0_CTRL 0x00001140 361 /* Intel Flash */ 362 #define CONFIG_SYS_CS1_BASE 0x00000000 363 #define CONFIG_SYS_CS1_MASK 0x01FF0001 364 #define CONFIG_SYS_CS1_CTRL 0x00000D60 365 366 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE 367 #else 368 /* Intel Flash */ 369 #define CONFIG_SYS_CS0_BASE 0x00000000 370 #define CONFIG_SYS_CS0_MASK 0x01FF0001 371 #define CONFIG_SYS_CS0_CTRL 0x00000D60 372 /* Atmel Flash */ 373 #define CONFIG_SYS_CS1_BASE 0x04000000 374 #define CONFIG_SYS_CS1_MASK 0x00070001 375 #define CONFIG_SYS_CS1_CTRL 0x00001140 376 377 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE 378 #endif 379 380 /* CPLD */ 381 #define CONFIG_SYS_CS2_BASE 0x08000000 382 #define CONFIG_SYS_CS2_MASK 0x00070001 383 #define CONFIG_SYS_CS2_CTRL 0x003f1140 384 385 /* FPGA */ 386 #define CONFIG_SYS_CS3_BASE 0x09000000 387 #define CONFIG_SYS_CS3_MASK 0x00070001 388 #define CONFIG_SYS_CS3_CTRL 0x00000020 389 390 #endif /* _M54455EVB_H */ 391