1 /* 2 * Configuation settings for the Freescale MCF54455 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54455EVB_H 15 #define _M54455EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54455EVB /* M54455EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 26 #undef CONFIG_WATCHDOG 27 28 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 29 30 /* 31 * BOOTP options 32 */ 33 #define CONFIG_BOOTP_BOOTFILESIZE 34 #define CONFIG_BOOTP_BOOTPATH 35 #define CONFIG_BOOTP_GATEWAY 36 #define CONFIG_BOOTP_HOSTNAME 37 38 /* Command line configuration */ 39 #undef CONFIG_CMD_PCI 40 41 /* Network configuration */ 42 #define CONFIG_MCFFEC 43 #ifdef CONFIG_MCFFEC 44 # define CONFIG_MII 1 45 # define CONFIG_MII_INIT 1 46 # define CONFIG_SYS_DISCOVER_PHY 47 # define CONFIG_SYS_RX_ETH_BUFFER 8 48 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 49 50 # define CONFIG_SYS_FEC0_PINMUX 0 51 # define CONFIG_SYS_FEC1_PINMUX 0 52 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 53 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 54 # define MCFFEC_TOUT_LOOP 50000 55 # define CONFIG_HAS_ETH1 56 57 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" 58 # define CONFIG_ETHPRIME "FEC0" 59 # define CONFIG_IPADDR 192.162.1.2 60 # define CONFIG_NETMASK 255.255.255.0 61 # define CONFIG_SERVERIP 192.162.1.1 62 # define CONFIG_GATEWAYIP 192.162.1.1 63 64 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 65 # ifndef CONFIG_SYS_DISCOVER_PHY 66 # define FECDUPLEX FULL 67 # define FECSPEED _100BASET 68 # else 69 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 70 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 71 # endif 72 # endif /* CONFIG_SYS_DISCOVER_PHY */ 73 #endif 74 75 #define CONFIG_HOSTNAME M54455EVB 76 #ifdef CONFIG_SYS_STMICRO_BOOT 77 /* ST Micro serial flash */ 78 #define CONFIG_SYS_LOAD_ADDR2 0x40010013 79 #define CONFIG_EXTRA_ENV_SETTINGS \ 80 "netdev=eth0\0" \ 81 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 82 "loadaddr=0x40010000\0" \ 83 "sbfhdr=sbfhdr.bin\0" \ 84 "uboot=u-boot.bin\0" \ 85 "load=tftp ${loadaddr} ${sbfhdr};" \ 86 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 87 "upd=run load; run prog\0" \ 88 "prog=sf probe 0:1 1000000 3;" \ 89 "sf erase 0 30000;" \ 90 "sf write ${loadaddr} 0 0x30000;" \ 91 "save\0" \ 92 "" 93 #else 94 /* Atmel and Intel */ 95 #ifdef CONFIG_SYS_ATMEL_BOOT 96 # define CONFIG_SYS_UBOOT_END 0x0403FFFF 97 #elif defined(CONFIG_SYS_INTEL_BOOT) 98 # define CONFIG_SYS_UBOOT_END 0x3FFFF 99 #endif 100 #define CONFIG_EXTRA_ENV_SETTINGS \ 101 "netdev=eth0\0" \ 102 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 103 "loadaddr=0x40010000\0" \ 104 "uboot=u-boot.bin\0" \ 105 "load=tftp ${loadaddr} ${uboot}\0" \ 106 "upd=run load; run prog\0" \ 107 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 108 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 109 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 110 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 111 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 112 " ${filesize}; save\0" \ 113 "" 114 #endif 115 116 /* ATA configuration */ 117 #define CONFIG_IDE_RESET 1 118 #define CONFIG_IDE_PREINIT 1 119 #define CONFIG_ATAPI 120 #undef CONFIG_LBA48 121 122 #define CONFIG_SYS_IDE_MAXBUS 1 123 #define CONFIG_SYS_IDE_MAXDEVICE 2 124 125 #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 126 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 127 128 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 129 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 130 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 131 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 132 133 /* Realtime clock */ 134 #define CONFIG_MCFRTC 135 #undef RTC_DEBUG 136 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 137 138 /* Timer */ 139 #define CONFIG_MCFTMR 140 #undef CONFIG_MCFPIT 141 142 /* I2c */ 143 #define CONFIG_SYS_I2C 144 #define CONFIG_SYS_I2C_FSL 145 #define CONFIG_SYS_FSL_I2C_SPEED 80000 146 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 147 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 148 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 149 150 /* DSPI and Serial Flash */ 151 #define CONFIG_CF_SPI 152 #define CONFIG_CF_DSPI 153 #define CONFIG_HARD_SPI 154 #define CONFIG_SYS_SBFHDR_SIZE 0x13 155 #ifdef CONFIG_CMD_SPI 156 157 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 158 DSPI_CTAR_PCSSCK_1CLK | \ 159 DSPI_CTAR_PASC(0) | \ 160 DSPI_CTAR_PDT(0) | \ 161 DSPI_CTAR_CSSCK(0) | \ 162 DSPI_CTAR_ASC(0) | \ 163 DSPI_CTAR_DT(1)) 164 #endif 165 166 /* PCI */ 167 #ifdef CONFIG_CMD_PCI 168 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 169 170 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 171 172 #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 173 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 174 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 175 176 #define CONFIG_SYS_PCI_IO_BUS 0xB1000000 177 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 178 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 179 180 #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 181 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 182 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 183 #endif 184 185 /* FPGA - Spartan 2 */ 186 /* experiment 187 #define CONFIG_FPGA 188 #define CONFIG_FPGA_COUNT 1 189 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 190 #define CONFIG_SYS_FPGA_CHECK_CTRLC 191 */ 192 193 /* Input, PCI, Flexbus, and VCO */ 194 #define CONFIG_EXTRA_CLOCK 195 196 #define CONFIG_PRAM 2048 /* 2048 KB */ 197 198 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 199 200 #if defined(CONFIG_CMD_KGDB) 201 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 202 #else 203 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 204 #endif 205 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 206 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 207 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 208 209 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 210 211 #define CONFIG_SYS_MBAR 0xFC000000 212 213 /* 214 * Low Level Configuration Settings 215 * (address mappings, register initial values, etc.) 216 * You should know what you are doing if you make changes here. 217 */ 218 219 /*----------------------------------------------------------------------- 220 * Definitions for initial stack pointer and data area (in DPRAM) 221 */ 222 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 223 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 224 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 225 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 226 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 227 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 228 229 /*----------------------------------------------------------------------- 230 * Start addresses for the final memory configuration 231 * (Set up by the startup code) 232 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 233 */ 234 #define CONFIG_SYS_SDRAM_BASE 0x40000000 235 #define CONFIG_SYS_SDRAM_BASE1 0x48000000 236 #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ 237 #define CONFIG_SYS_SDRAM_CFG1 0x65311610 238 #define CONFIG_SYS_SDRAM_CFG2 0x59670000 239 #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 240 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 241 #define CONFIG_SYS_SDRAM_MODE 0x00010033 242 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA 243 244 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 245 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 246 247 #ifdef CONFIG_CF_SBF 248 # define CONFIG_SERIAL_BOOT 249 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 250 #else 251 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 252 #endif 253 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 254 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 255 256 /* Reserve 256 kB for malloc() */ 257 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 258 259 /* 260 * For booting Linux, the board info and command line data 261 * have to be in the first 8 MB of memory, since this is 262 * the maximum mapped by the Linux kernel during initialization ?? 263 */ 264 /* Initial Memory map for Linux */ 265 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 266 267 /* 268 * Configuration for environment 269 * Environment is not embedded in u-boot. First time runing may have env 270 * crc error warning if there is no correct environment on the flash. 271 */ 272 #ifdef CONFIG_CF_SBF 273 # define CONFIG_ENV_IS_IN_SPI_FLASH 274 # define CONFIG_ENV_SPI_CS 1 275 #endif 276 #undef CONFIG_ENV_OVERWRITE 277 278 /*----------------------------------------------------------------------- 279 * FLASH organization 280 */ 281 #ifdef CONFIG_SYS_STMICRO_BOOT 282 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 283 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE 284 # define CONFIG_ENV_OFFSET 0x30000 285 # define CONFIG_ENV_SIZE 0x2000 286 # define CONFIG_ENV_SECT_SIZE 0x10000 287 #endif 288 #ifdef CONFIG_SYS_ATMEL_BOOT 289 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 290 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 291 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 292 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 293 # define CONFIG_ENV_SIZE 0x2000 294 # define CONFIG_ENV_SECT_SIZE 0x10000 295 #endif 296 #ifdef CONFIG_SYS_INTEL_BOOT 297 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 298 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 299 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 300 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 301 # define CONFIG_ENV_SIZE 0x2000 302 # define CONFIG_ENV_SECT_SIZE 0x20000 303 #endif 304 305 #define CONFIG_SYS_FLASH_CFI 306 #ifdef CONFIG_SYS_FLASH_CFI 307 308 # define CONFIG_FLASH_CFI_DRIVER 1 309 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 310 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 311 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 312 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 313 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 314 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 315 # define CONFIG_SYS_FLASH_CHECKSUM 316 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 317 # define CONFIG_FLASH_CFI_LEGACY 318 319 #ifdef CONFIG_FLASH_CFI_LEGACY 320 # define CONFIG_SYS_ATMEL_REGION 4 321 # define CONFIG_SYS_ATMEL_TOTALSECT 11 322 # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} 323 # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 324 #endif 325 #endif 326 327 /* 328 * This is setting for JFFS2 support in u-boot. 329 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 330 */ 331 #ifdef CONFIG_CMD_JFFS2 332 #ifdef CF_STMICRO_BOOT 333 # define CONFIG_JFFS2_DEV "nor1" 334 # define CONFIG_JFFS2_PART_SIZE 0x01000000 335 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) 336 #endif 337 #ifdef CONFIG_SYS_ATMEL_BOOT 338 # define CONFIG_JFFS2_DEV "nor1" 339 # define CONFIG_JFFS2_PART_SIZE 0x01000000 340 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) 341 #endif 342 #ifdef CONFIG_SYS_INTEL_BOOT 343 # define CONFIG_JFFS2_DEV "nor0" 344 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 345 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 346 #endif 347 #endif 348 349 /*----------------------------------------------------------------------- 350 * Cache Configuration 351 */ 352 #define CONFIG_SYS_CACHELINE_SIZE 16 353 354 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 355 CONFIG_SYS_INIT_RAM_SIZE - 8) 356 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 357 CONFIG_SYS_INIT_RAM_SIZE - 4) 358 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 359 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 360 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 361 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 362 CF_ACR_EN | CF_ACR_SM_ALL) 363 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 364 CF_CACR_ICINVA | CF_CACR_EUSP) 365 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 366 CF_CACR_DEC | CF_CACR_DDCM_P | \ 367 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 368 369 /*----------------------------------------------------------------------- 370 * Memory bank definitions 371 */ 372 /* 373 * CS0 - NOR Flash 1, 2, 4, or 8MB 374 * CS1 - CompactFlash and registers 375 * CS2 - CPLD 376 * CS3 - FPGA 377 * CS4 - Available 378 * CS5 - Available 379 */ 380 381 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) 382 /* Atmel Flash */ 383 #define CONFIG_SYS_CS0_BASE 0x04000000 384 #define CONFIG_SYS_CS0_MASK 0x00070001 385 #define CONFIG_SYS_CS0_CTRL 0x00001140 386 /* Intel Flash */ 387 #define CONFIG_SYS_CS1_BASE 0x00000000 388 #define CONFIG_SYS_CS1_MASK 0x01FF0001 389 #define CONFIG_SYS_CS1_CTRL 0x00000D60 390 391 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE 392 #else 393 /* Intel Flash */ 394 #define CONFIG_SYS_CS0_BASE 0x00000000 395 #define CONFIG_SYS_CS0_MASK 0x01FF0001 396 #define CONFIG_SYS_CS0_CTRL 0x00000D60 397 /* Atmel Flash */ 398 #define CONFIG_SYS_CS1_BASE 0x04000000 399 #define CONFIG_SYS_CS1_MASK 0x00070001 400 #define CONFIG_SYS_CS1_CTRL 0x00001140 401 402 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE 403 #endif 404 405 /* CPLD */ 406 #define CONFIG_SYS_CS2_BASE 0x08000000 407 #define CONFIG_SYS_CS2_MASK 0x00070001 408 #define CONFIG_SYS_CS2_CTRL 0x003f1140 409 410 /* FPGA */ 411 #define CONFIG_SYS_CS3_BASE 0x09000000 412 #define CONFIG_SYS_CS3_MASK 0x00070001 413 #define CONFIG_SYS_CS3_CTRL 0x00000020 414 415 #endif /* _M54455EVB_H */ 416