1 /* 2 * Configuation settings for the Freescale MCF54455 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54455EVB_H 15 #define _M54455EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54455EVB /* M54455EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 26 #undef CONFIG_WATCHDOG 27 28 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 29 30 /* 31 * BOOTP options 32 */ 33 #define CONFIG_BOOTP_BOOTFILESIZE 34 #define CONFIG_BOOTP_BOOTPATH 35 #define CONFIG_BOOTP_GATEWAY 36 #define CONFIG_BOOTP_HOSTNAME 37 38 /* Command line configuration */ 39 #define CONFIG_CMD_DATE 40 #define CONFIG_CMD_IDE 41 #define CONFIG_CMD_JFFS2 42 #undef CONFIG_CMD_PCI 43 #define CONFIG_CMD_REGINFO 44 45 /* Network configuration */ 46 #define CONFIG_MCFFEC 47 #ifdef CONFIG_MCFFEC 48 # define CONFIG_MII 1 49 # define CONFIG_MII_INIT 1 50 # define CONFIG_SYS_DISCOVER_PHY 51 # define CONFIG_SYS_RX_ETH_BUFFER 8 52 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 53 54 # define CONFIG_SYS_FEC0_PINMUX 0 55 # define CONFIG_SYS_FEC1_PINMUX 0 56 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 57 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 58 # define MCFFEC_TOUT_LOOP 50000 59 # define CONFIG_HAS_ETH1 60 61 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" 62 # define CONFIG_ETHPRIME "FEC0" 63 # define CONFIG_IPADDR 192.162.1.2 64 # define CONFIG_NETMASK 255.255.255.0 65 # define CONFIG_SERVERIP 192.162.1.1 66 # define CONFIG_GATEWAYIP 192.162.1.1 67 68 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 69 # ifndef CONFIG_SYS_DISCOVER_PHY 70 # define FECDUPLEX FULL 71 # define FECSPEED _100BASET 72 # else 73 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 74 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 75 # endif 76 # endif /* CONFIG_SYS_DISCOVER_PHY */ 77 #endif 78 79 #define CONFIG_HOSTNAME M54455EVB 80 #ifdef CONFIG_SYS_STMICRO_BOOT 81 /* ST Micro serial flash */ 82 #define CONFIG_SYS_LOAD_ADDR2 0x40010013 83 #define CONFIG_EXTRA_ENV_SETTINGS \ 84 "netdev=eth0\0" \ 85 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 86 "loadaddr=0x40010000\0" \ 87 "sbfhdr=sbfhdr.bin\0" \ 88 "uboot=u-boot.bin\0" \ 89 "load=tftp ${loadaddr} ${sbfhdr};" \ 90 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 91 "upd=run load; run prog\0" \ 92 "prog=sf probe 0:1 1000000 3;" \ 93 "sf erase 0 30000;" \ 94 "sf write ${loadaddr} 0 0x30000;" \ 95 "save\0" \ 96 "" 97 #else 98 /* Atmel and Intel */ 99 #ifdef CONFIG_SYS_ATMEL_BOOT 100 # define CONFIG_SYS_UBOOT_END 0x0403FFFF 101 #elif defined(CONFIG_SYS_INTEL_BOOT) 102 # define CONFIG_SYS_UBOOT_END 0x3FFFF 103 #endif 104 #define CONFIG_EXTRA_ENV_SETTINGS \ 105 "netdev=eth0\0" \ 106 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 107 "loadaddr=0x40010000\0" \ 108 "uboot=u-boot.bin\0" \ 109 "load=tftp ${loadaddr} ${uboot}\0" \ 110 "upd=run load; run prog\0" \ 111 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 112 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 113 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 114 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 115 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 116 " ${filesize}; save\0" \ 117 "" 118 #endif 119 120 /* ATA configuration */ 121 #define CONFIG_IDE_RESET 1 122 #define CONFIG_IDE_PREINIT 1 123 #define CONFIG_ATAPI 124 #undef CONFIG_LBA48 125 126 #define CONFIG_SYS_IDE_MAXBUS 1 127 #define CONFIG_SYS_IDE_MAXDEVICE 2 128 129 #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 130 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 131 132 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 133 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 134 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 135 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 136 137 /* Realtime clock */ 138 #define CONFIG_MCFRTC 139 #undef RTC_DEBUG 140 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 141 142 /* Timer */ 143 #define CONFIG_MCFTMR 144 #undef CONFIG_MCFPIT 145 146 /* I2c */ 147 #define CONFIG_SYS_I2C 148 #define CONFIG_SYS_I2C_FSL 149 #define CONFIG_SYS_FSL_I2C_SPEED 80000 150 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 151 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 152 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 153 154 /* DSPI and Serial Flash */ 155 #define CONFIG_CF_SPI 156 #define CONFIG_CF_DSPI 157 #define CONFIG_HARD_SPI 158 #define CONFIG_SYS_SBFHDR_SIZE 0x13 159 #ifdef CONFIG_CMD_SPI 160 161 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 162 DSPI_CTAR_PCSSCK_1CLK | \ 163 DSPI_CTAR_PASC(0) | \ 164 DSPI_CTAR_PDT(0) | \ 165 DSPI_CTAR_CSSCK(0) | \ 166 DSPI_CTAR_ASC(0) | \ 167 DSPI_CTAR_DT(1)) 168 #endif 169 170 /* PCI */ 171 #ifdef CONFIG_CMD_PCI 172 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 173 174 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 175 176 #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 177 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 178 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 179 180 #define CONFIG_SYS_PCI_IO_BUS 0xB1000000 181 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 182 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 183 184 #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 185 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 186 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 187 #endif 188 189 /* FPGA - Spartan 2 */ 190 /* experiment 191 #define CONFIG_FPGA 192 #define CONFIG_FPGA_COUNT 1 193 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 194 #define CONFIG_SYS_FPGA_CHECK_CTRLC 195 */ 196 197 /* Input, PCI, Flexbus, and VCO */ 198 #define CONFIG_EXTRA_CLOCK 199 200 #define CONFIG_PRAM 2048 /* 2048 KB */ 201 202 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 203 204 #if defined(CONFIG_CMD_KGDB) 205 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 206 #else 207 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 208 #endif 209 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 210 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 211 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 212 213 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 214 215 #define CONFIG_SYS_MBAR 0xFC000000 216 217 /* 218 * Low Level Configuration Settings 219 * (address mappings, register initial values, etc.) 220 * You should know what you are doing if you make changes here. 221 */ 222 223 /*----------------------------------------------------------------------- 224 * Definitions for initial stack pointer and data area (in DPRAM) 225 */ 226 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 227 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 228 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 229 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 230 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 231 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 232 233 /*----------------------------------------------------------------------- 234 * Start addresses for the final memory configuration 235 * (Set up by the startup code) 236 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 237 */ 238 #define CONFIG_SYS_SDRAM_BASE 0x40000000 239 #define CONFIG_SYS_SDRAM_BASE1 0x48000000 240 #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ 241 #define CONFIG_SYS_SDRAM_CFG1 0x65311610 242 #define CONFIG_SYS_SDRAM_CFG2 0x59670000 243 #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 244 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 245 #define CONFIG_SYS_SDRAM_MODE 0x00010033 246 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA 247 248 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 249 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 250 251 #ifdef CONFIG_CF_SBF 252 # define CONFIG_SERIAL_BOOT 253 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 254 #else 255 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 256 #endif 257 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 258 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 259 260 /* Reserve 256 kB for malloc() */ 261 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 262 263 /* 264 * For booting Linux, the board info and command line data 265 * have to be in the first 8 MB of memory, since this is 266 * the maximum mapped by the Linux kernel during initialization ?? 267 */ 268 /* Initial Memory map for Linux */ 269 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 270 271 /* 272 * Configuration for environment 273 * Environment is not embedded in u-boot. First time runing may have env 274 * crc error warning if there is no correct environment on the flash. 275 */ 276 #ifdef CONFIG_CF_SBF 277 # define CONFIG_ENV_IS_IN_SPI_FLASH 278 # define CONFIG_ENV_SPI_CS 1 279 #else 280 # define CONFIG_ENV_IS_IN_FLASH 1 281 #endif 282 #undef CONFIG_ENV_OVERWRITE 283 284 /*----------------------------------------------------------------------- 285 * FLASH organization 286 */ 287 #ifdef CONFIG_SYS_STMICRO_BOOT 288 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 289 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE 290 # define CONFIG_ENV_OFFSET 0x30000 291 # define CONFIG_ENV_SIZE 0x2000 292 # define CONFIG_ENV_SECT_SIZE 0x10000 293 #endif 294 #ifdef CONFIG_SYS_ATMEL_BOOT 295 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 296 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 297 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 298 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 299 # define CONFIG_ENV_SIZE 0x2000 300 # define CONFIG_ENV_SECT_SIZE 0x10000 301 #endif 302 #ifdef CONFIG_SYS_INTEL_BOOT 303 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 304 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 305 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 306 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 307 # define CONFIG_ENV_SIZE 0x2000 308 # define CONFIG_ENV_SECT_SIZE 0x20000 309 #endif 310 311 #define CONFIG_SYS_FLASH_CFI 312 #ifdef CONFIG_SYS_FLASH_CFI 313 314 # define CONFIG_FLASH_CFI_DRIVER 1 315 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 316 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 317 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 318 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 319 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 320 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 321 # define CONFIG_SYS_FLASH_CHECKSUM 322 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 323 # define CONFIG_FLASH_CFI_LEGACY 324 325 #ifdef CONFIG_FLASH_CFI_LEGACY 326 # define CONFIG_SYS_ATMEL_REGION 4 327 # define CONFIG_SYS_ATMEL_TOTALSECT 11 328 # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} 329 # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 330 #endif 331 #endif 332 333 /* 334 * This is setting for JFFS2 support in u-boot. 335 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 336 */ 337 #ifdef CONFIG_CMD_JFFS2 338 #ifdef CF_STMICRO_BOOT 339 # define CONFIG_JFFS2_DEV "nor1" 340 # define CONFIG_JFFS2_PART_SIZE 0x01000000 341 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) 342 #endif 343 #ifdef CONFIG_SYS_ATMEL_BOOT 344 # define CONFIG_JFFS2_DEV "nor1" 345 # define CONFIG_JFFS2_PART_SIZE 0x01000000 346 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) 347 #endif 348 #ifdef CONFIG_SYS_INTEL_BOOT 349 # define CONFIG_JFFS2_DEV "nor0" 350 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 351 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 352 #endif 353 #endif 354 355 /*----------------------------------------------------------------------- 356 * Cache Configuration 357 */ 358 #define CONFIG_SYS_CACHELINE_SIZE 16 359 360 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 361 CONFIG_SYS_INIT_RAM_SIZE - 8) 362 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 363 CONFIG_SYS_INIT_RAM_SIZE - 4) 364 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 365 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 366 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 367 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 368 CF_ACR_EN | CF_ACR_SM_ALL) 369 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 370 CF_CACR_ICINVA | CF_CACR_EUSP) 371 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 372 CF_CACR_DEC | CF_CACR_DDCM_P | \ 373 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 374 375 /*----------------------------------------------------------------------- 376 * Memory bank definitions 377 */ 378 /* 379 * CS0 - NOR Flash 1, 2, 4, or 8MB 380 * CS1 - CompactFlash and registers 381 * CS2 - CPLD 382 * CS3 - FPGA 383 * CS4 - Available 384 * CS5 - Available 385 */ 386 387 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) 388 /* Atmel Flash */ 389 #define CONFIG_SYS_CS0_BASE 0x04000000 390 #define CONFIG_SYS_CS0_MASK 0x00070001 391 #define CONFIG_SYS_CS0_CTRL 0x00001140 392 /* Intel Flash */ 393 #define CONFIG_SYS_CS1_BASE 0x00000000 394 #define CONFIG_SYS_CS1_MASK 0x01FF0001 395 #define CONFIG_SYS_CS1_CTRL 0x00000D60 396 397 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE 398 #else 399 /* Intel Flash */ 400 #define CONFIG_SYS_CS0_BASE 0x00000000 401 #define CONFIG_SYS_CS0_MASK 0x01FF0001 402 #define CONFIG_SYS_CS0_CTRL 0x00000D60 403 /* Atmel Flash */ 404 #define CONFIG_SYS_CS1_BASE 0x04000000 405 #define CONFIG_SYS_CS1_MASK 0x00070001 406 #define CONFIG_SYS_CS1_CTRL 0x00001140 407 408 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE 409 #endif 410 411 /* CPLD */ 412 #define CONFIG_SYS_CS2_BASE 0x08000000 413 #define CONFIG_SYS_CS2_MASK 0x00070001 414 #define CONFIG_SYS_CS2_CTRL 0x003f1140 415 416 /* FPGA */ 417 #define CONFIG_SYS_CS3_BASE 0x09000000 418 #define CONFIG_SYS_CS3_MASK 0x00070001 419 #define CONFIG_SYS_CS3_CTRL 0x00000020 420 421 #endif /* _M54455EVB_H */ 422