1 /* 2 * Configuation settings for the Freescale MCF54455 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54455EVB_H 15 #define _M54455EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54455EVB /* M54455EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 26 #undef CONFIG_WATCHDOG 27 28 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 29 30 /* 31 * BOOTP options 32 */ 33 #define CONFIG_BOOTP_BOOTFILESIZE 34 #define CONFIG_BOOTP_BOOTPATH 35 #define CONFIG_BOOTP_GATEWAY 36 #define CONFIG_BOOTP_HOSTNAME 37 38 /* Command line configuration */ 39 #undef CONFIG_CMD_PCI 40 #define CONFIG_CMD_REGINFO 41 42 /* Network configuration */ 43 #define CONFIG_MCFFEC 44 #ifdef CONFIG_MCFFEC 45 # define CONFIG_MII 1 46 # define CONFIG_MII_INIT 1 47 # define CONFIG_SYS_DISCOVER_PHY 48 # define CONFIG_SYS_RX_ETH_BUFFER 8 49 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 50 51 # define CONFIG_SYS_FEC0_PINMUX 0 52 # define CONFIG_SYS_FEC1_PINMUX 0 53 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 54 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 55 # define MCFFEC_TOUT_LOOP 50000 56 # define CONFIG_HAS_ETH1 57 58 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" 59 # define CONFIG_ETHPRIME "FEC0" 60 # define CONFIG_IPADDR 192.162.1.2 61 # define CONFIG_NETMASK 255.255.255.0 62 # define CONFIG_SERVERIP 192.162.1.1 63 # define CONFIG_GATEWAYIP 192.162.1.1 64 65 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 66 # ifndef CONFIG_SYS_DISCOVER_PHY 67 # define FECDUPLEX FULL 68 # define FECSPEED _100BASET 69 # else 70 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 71 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 72 # endif 73 # endif /* CONFIG_SYS_DISCOVER_PHY */ 74 #endif 75 76 #define CONFIG_HOSTNAME M54455EVB 77 #ifdef CONFIG_SYS_STMICRO_BOOT 78 /* ST Micro serial flash */ 79 #define CONFIG_SYS_LOAD_ADDR2 0x40010013 80 #define CONFIG_EXTRA_ENV_SETTINGS \ 81 "netdev=eth0\0" \ 82 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 83 "loadaddr=0x40010000\0" \ 84 "sbfhdr=sbfhdr.bin\0" \ 85 "uboot=u-boot.bin\0" \ 86 "load=tftp ${loadaddr} ${sbfhdr};" \ 87 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 88 "upd=run load; run prog\0" \ 89 "prog=sf probe 0:1 1000000 3;" \ 90 "sf erase 0 30000;" \ 91 "sf write ${loadaddr} 0 0x30000;" \ 92 "save\0" \ 93 "" 94 #else 95 /* Atmel and Intel */ 96 #ifdef CONFIG_SYS_ATMEL_BOOT 97 # define CONFIG_SYS_UBOOT_END 0x0403FFFF 98 #elif defined(CONFIG_SYS_INTEL_BOOT) 99 # define CONFIG_SYS_UBOOT_END 0x3FFFF 100 #endif 101 #define CONFIG_EXTRA_ENV_SETTINGS \ 102 "netdev=eth0\0" \ 103 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 104 "loadaddr=0x40010000\0" \ 105 "uboot=u-boot.bin\0" \ 106 "load=tftp ${loadaddr} ${uboot}\0" \ 107 "upd=run load; run prog\0" \ 108 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 109 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 110 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 111 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 112 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 113 " ${filesize}; save\0" \ 114 "" 115 #endif 116 117 /* ATA configuration */ 118 #define CONFIG_IDE_RESET 1 119 #define CONFIG_IDE_PREINIT 1 120 #define CONFIG_ATAPI 121 #undef CONFIG_LBA48 122 123 #define CONFIG_SYS_IDE_MAXBUS 1 124 #define CONFIG_SYS_IDE_MAXDEVICE 2 125 126 #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 127 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 128 129 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 130 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 131 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 132 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 133 134 /* Realtime clock */ 135 #define CONFIG_MCFRTC 136 #undef RTC_DEBUG 137 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 138 139 /* Timer */ 140 #define CONFIG_MCFTMR 141 #undef CONFIG_MCFPIT 142 143 /* I2c */ 144 #define CONFIG_SYS_I2C 145 #define CONFIG_SYS_I2C_FSL 146 #define CONFIG_SYS_FSL_I2C_SPEED 80000 147 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 148 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 149 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 150 151 /* DSPI and Serial Flash */ 152 #define CONFIG_CF_SPI 153 #define CONFIG_CF_DSPI 154 #define CONFIG_HARD_SPI 155 #define CONFIG_SYS_SBFHDR_SIZE 0x13 156 #ifdef CONFIG_CMD_SPI 157 158 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 159 DSPI_CTAR_PCSSCK_1CLK | \ 160 DSPI_CTAR_PASC(0) | \ 161 DSPI_CTAR_PDT(0) | \ 162 DSPI_CTAR_CSSCK(0) | \ 163 DSPI_CTAR_ASC(0) | \ 164 DSPI_CTAR_DT(1)) 165 #endif 166 167 /* PCI */ 168 #ifdef CONFIG_CMD_PCI 169 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 170 171 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 172 173 #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 174 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 175 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 176 177 #define CONFIG_SYS_PCI_IO_BUS 0xB1000000 178 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 179 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 180 181 #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 182 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 183 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 184 #endif 185 186 /* FPGA - Spartan 2 */ 187 /* experiment 188 #define CONFIG_FPGA 189 #define CONFIG_FPGA_COUNT 1 190 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 191 #define CONFIG_SYS_FPGA_CHECK_CTRLC 192 */ 193 194 /* Input, PCI, Flexbus, and VCO */ 195 #define CONFIG_EXTRA_CLOCK 196 197 #define CONFIG_PRAM 2048 /* 2048 KB */ 198 199 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 200 201 #if defined(CONFIG_CMD_KGDB) 202 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 203 #else 204 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 205 #endif 206 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 207 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 208 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 209 210 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 211 212 #define CONFIG_SYS_MBAR 0xFC000000 213 214 /* 215 * Low Level Configuration Settings 216 * (address mappings, register initial values, etc.) 217 * You should know what you are doing if you make changes here. 218 */ 219 220 /*----------------------------------------------------------------------- 221 * Definitions for initial stack pointer and data area (in DPRAM) 222 */ 223 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 224 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 225 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 226 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 227 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 228 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 229 230 /*----------------------------------------------------------------------- 231 * Start addresses for the final memory configuration 232 * (Set up by the startup code) 233 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 234 */ 235 #define CONFIG_SYS_SDRAM_BASE 0x40000000 236 #define CONFIG_SYS_SDRAM_BASE1 0x48000000 237 #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ 238 #define CONFIG_SYS_SDRAM_CFG1 0x65311610 239 #define CONFIG_SYS_SDRAM_CFG2 0x59670000 240 #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 241 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 242 #define CONFIG_SYS_SDRAM_MODE 0x00010033 243 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA 244 245 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 246 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 247 248 #ifdef CONFIG_CF_SBF 249 # define CONFIG_SERIAL_BOOT 250 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 251 #else 252 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 253 #endif 254 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 255 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 256 257 /* Reserve 256 kB for malloc() */ 258 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 259 260 /* 261 * For booting Linux, the board info and command line data 262 * have to be in the first 8 MB of memory, since this is 263 * the maximum mapped by the Linux kernel during initialization ?? 264 */ 265 /* Initial Memory map for Linux */ 266 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 267 268 /* 269 * Configuration for environment 270 * Environment is not embedded in u-boot. First time runing may have env 271 * crc error warning if there is no correct environment on the flash. 272 */ 273 #ifdef CONFIG_CF_SBF 274 # define CONFIG_ENV_IS_IN_SPI_FLASH 275 # define CONFIG_ENV_SPI_CS 1 276 #else 277 # define CONFIG_ENV_IS_IN_FLASH 1 278 #endif 279 #undef CONFIG_ENV_OVERWRITE 280 281 /*----------------------------------------------------------------------- 282 * FLASH organization 283 */ 284 #ifdef CONFIG_SYS_STMICRO_BOOT 285 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 286 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE 287 # define CONFIG_ENV_OFFSET 0x30000 288 # define CONFIG_ENV_SIZE 0x2000 289 # define CONFIG_ENV_SECT_SIZE 0x10000 290 #endif 291 #ifdef CONFIG_SYS_ATMEL_BOOT 292 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 293 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 294 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 295 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 296 # define CONFIG_ENV_SIZE 0x2000 297 # define CONFIG_ENV_SECT_SIZE 0x10000 298 #endif 299 #ifdef CONFIG_SYS_INTEL_BOOT 300 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 301 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 302 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 303 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 304 # define CONFIG_ENV_SIZE 0x2000 305 # define CONFIG_ENV_SECT_SIZE 0x20000 306 #endif 307 308 #define CONFIG_SYS_FLASH_CFI 309 #ifdef CONFIG_SYS_FLASH_CFI 310 311 # define CONFIG_FLASH_CFI_DRIVER 1 312 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 313 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 314 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 315 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 316 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 317 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 318 # define CONFIG_SYS_FLASH_CHECKSUM 319 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 320 # define CONFIG_FLASH_CFI_LEGACY 321 322 #ifdef CONFIG_FLASH_CFI_LEGACY 323 # define CONFIG_SYS_ATMEL_REGION 4 324 # define CONFIG_SYS_ATMEL_TOTALSECT 11 325 # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} 326 # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 327 #endif 328 #endif 329 330 /* 331 * This is setting for JFFS2 support in u-boot. 332 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 333 */ 334 #ifdef CONFIG_CMD_JFFS2 335 #ifdef CF_STMICRO_BOOT 336 # define CONFIG_JFFS2_DEV "nor1" 337 # define CONFIG_JFFS2_PART_SIZE 0x01000000 338 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) 339 #endif 340 #ifdef CONFIG_SYS_ATMEL_BOOT 341 # define CONFIG_JFFS2_DEV "nor1" 342 # define CONFIG_JFFS2_PART_SIZE 0x01000000 343 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) 344 #endif 345 #ifdef CONFIG_SYS_INTEL_BOOT 346 # define CONFIG_JFFS2_DEV "nor0" 347 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 348 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 349 #endif 350 #endif 351 352 /*----------------------------------------------------------------------- 353 * Cache Configuration 354 */ 355 #define CONFIG_SYS_CACHELINE_SIZE 16 356 357 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 358 CONFIG_SYS_INIT_RAM_SIZE - 8) 359 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 360 CONFIG_SYS_INIT_RAM_SIZE - 4) 361 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 362 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 363 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 364 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 365 CF_ACR_EN | CF_ACR_SM_ALL) 366 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 367 CF_CACR_ICINVA | CF_CACR_EUSP) 368 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 369 CF_CACR_DEC | CF_CACR_DDCM_P | \ 370 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 371 372 /*----------------------------------------------------------------------- 373 * Memory bank definitions 374 */ 375 /* 376 * CS0 - NOR Flash 1, 2, 4, or 8MB 377 * CS1 - CompactFlash and registers 378 * CS2 - CPLD 379 * CS3 - FPGA 380 * CS4 - Available 381 * CS5 - Available 382 */ 383 384 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) 385 /* Atmel Flash */ 386 #define CONFIG_SYS_CS0_BASE 0x04000000 387 #define CONFIG_SYS_CS0_MASK 0x00070001 388 #define CONFIG_SYS_CS0_CTRL 0x00001140 389 /* Intel Flash */ 390 #define CONFIG_SYS_CS1_BASE 0x00000000 391 #define CONFIG_SYS_CS1_MASK 0x01FF0001 392 #define CONFIG_SYS_CS1_CTRL 0x00000D60 393 394 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE 395 #else 396 /* Intel Flash */ 397 #define CONFIG_SYS_CS0_BASE 0x00000000 398 #define CONFIG_SYS_CS0_MASK 0x01FF0001 399 #define CONFIG_SYS_CS0_CTRL 0x00000D60 400 /* Atmel Flash */ 401 #define CONFIG_SYS_CS1_BASE 0x04000000 402 #define CONFIG_SYS_CS1_MASK 0x00070001 403 #define CONFIG_SYS_CS1_CTRL 0x00001140 404 405 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE 406 #endif 407 408 /* CPLD */ 409 #define CONFIG_SYS_CS2_BASE 0x08000000 410 #define CONFIG_SYS_CS2_MASK 0x00070001 411 #define CONFIG_SYS_CS2_CTRL 0x003f1140 412 413 /* FPGA */ 414 #define CONFIG_SYS_CS3_BASE 0x09000000 415 #define CONFIG_SYS_CS3_MASK 0x00070001 416 #define CONFIG_SYS_CS3_CTRL 0x00000020 417 418 #endif /* _M54455EVB_H */ 419