1 /* 2 * Configuation settings for the Freescale MCF54455 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef _M54455EVB_H 31 #define _M54455EVB_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_MCF5445x /* define processor family */ 38 #define CONFIG_M54455 /* define processor type */ 39 #define CONFIG_M54455EVB /* M54455EVB board */ 40 41 #define CONFIG_MCFUART 42 #define CFG_UART_PORT (0) 43 #define CONFIG_BAUDRATE 115200 44 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 45 46 #undef CONFIG_WATCHDOG 47 48 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 49 50 /* 51 * BOOTP options 52 */ 53 #define CONFIG_BOOTP_BOOTFILESIZE 54 #define CONFIG_BOOTP_BOOTPATH 55 #define CONFIG_BOOTP_GATEWAY 56 #define CONFIG_BOOTP_HOSTNAME 57 58 /* Command line configuration */ 59 #include <config_cmd_default.h> 60 61 #define CONFIG_CMD_BOOTD 62 #define CONFIG_CMD_CACHE 63 #define CONFIG_CMD_DATE 64 #define CONFIG_CMD_DHCP 65 #define CONFIG_CMD_ELF 66 #define CONFIG_CMD_EXT2 67 #define CONFIG_CMD_FAT 68 #define CONFIG_CMD_FLASH 69 #define CONFIG_CMD_I2C 70 #define CONFIG_CMD_IDE 71 #define CONFIG_CMD_JFFS2 72 #define CONFIG_CMD_MEMORY 73 #define CONFIG_CMD_MISC 74 #define CONFIG_CMD_MII 75 #define CONFIG_CMD_NET 76 #undef CONFIG_CMD_PCI 77 #define CONFIG_CMD_PING 78 #define CONFIG_CMD_REGINFO 79 80 #undef CONFIG_CMD_LOADB 81 #undef CONFIG_CMD_LOADS 82 83 /* Network configuration */ 84 #define CONFIG_MCFFEC 85 #ifdef CONFIG_MCFFEC 86 # define CONFIG_NET_MULTI 1 87 # define CONFIG_MII 1 88 # define CONFIG_MII_INIT 1 89 # define CFG_DISCOVER_PHY 90 # define CFG_RX_ETH_BUFFER 8 91 # define CFG_FAULT_ECHO_LINK_DOWN 92 93 # define CFG_FEC0_PINMUX 0 94 # define CFG_FEC1_PINMUX 0 95 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE 96 # define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE 97 # define MCFFEC_TOUT_LOOP 50000 98 # define CONFIG_HAS_ETH1 99 100 # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 101 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" 102 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 103 # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 104 # define CONFIG_ETHPRIME "FEC0" 105 # define CONFIG_IPADDR 192.162.1.2 106 # define CONFIG_NETMASK 255.255.255.0 107 # define CONFIG_SERVERIP 192.162.1.1 108 # define CONFIG_GATEWAYIP 192.162.1.1 109 # define CONFIG_OVERWRITE_ETHADDR_ONCE 110 111 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ 112 # ifndef CFG_DISCOVER_PHY 113 # define FECDUPLEX FULL 114 # define FECSPEED _100BASET 115 # else 116 # ifndef CFG_FAULT_ECHO_LINK_DOWN 117 # define CFG_FAULT_ECHO_LINK_DOWN 118 # endif 119 # endif /* CFG_DISCOVER_PHY */ 120 #endif 121 122 #define CONFIG_HOSTNAME M54455EVB 123 #define CONFIG_EXTRA_ENV_SETTINGS \ 124 "netdev=eth0\0" \ 125 "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ 126 "loadaddr=40010000\0" \ 127 "u-boot=u-boot.bin\0" \ 128 "load=tftp ${loadaddr) ${u-boot}\0" \ 129 "upd=run load; run prog\0" \ 130 "prog=prot off 4000000 402ffff;" \ 131 "era 4000000 402ffff;" \ 132 "cp.b ${loadaddr} 0 ${filesize};" \ 133 "save\0" \ 134 "" 135 136 /* ATA configuration */ 137 #define CONFIG_ISO_PARTITION 138 #define CONFIG_DOS_PARTITION 139 #define CONFIG_IDE_RESET 1 140 #define CONFIG_IDE_PREINIT 1 141 #define CONFIG_ATAPI 142 #undef CONFIG_LBA48 143 144 #define CFG_IDE_MAXBUS 1 145 #define CFG_IDE_MAXDEVICE 2 146 147 #define CFG_ATA_BASE_ADDR 0x90000000 148 #define CFG_ATA_IDE0_OFFSET 0 149 150 #define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 151 #define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 152 #define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 153 #define CFG_ATA_STRIDE 4 /* Interval between registers */ 154 #define _IO_BASE 0 155 156 /* Realtime clock */ 157 #define CONFIG_MCFRTC 158 #undef RTC_DEBUG 159 #define CFG_RTC_OSCILLATOR (32 * CFG_HZ) 160 161 /* Timer */ 162 #define CONFIG_MCFTMR 163 #undef CONFIG_MCFPIT 164 165 /* I2c */ 166 #define CONFIG_FSL_I2C 167 #define CONFIG_HARD_I2C /* I2C with hardware support */ 168 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 169 #define CFG_I2C_SPEED 80000 /* I2C speed and slave address */ 170 #define CFG_I2C_SLAVE 0x7F 171 #define CFG_I2C_OFFSET 0x58000 172 #define CFG_IMMR CFG_MBAR 173 174 /* DSPI and Serial Flash */ 175 #define CONFIG_CF_DSPI 176 #define CONFIG_SERIAL_FLASH 177 178 /* PCI */ 179 #ifdef CONFIG_CMD_PCI 180 #define CONFIG_PCI 1 181 #define CONFIG_PCI_PNP 1 182 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 183 184 #define CFG_PCI_CACHE_LINE_SIZE 4 185 186 #define CFG_PCI_MEM_BUS 0xA0000000 187 #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS 188 #define CFG_PCI_MEM_SIZE 0x10000000 189 190 #define CFG_PCI_IO_BUS 0xB1000000 191 #define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS 192 #define CFG_PCI_IO_SIZE 0x01000000 193 194 #define CFG_PCI_CFG_BUS 0xB0000000 195 #define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS 196 #define CFG_PCI_CFG_SIZE 0x01000000 197 #endif 198 199 /* FPGA - Spartan 2 */ 200 /* experiment 201 #define CONFIG_FPGA CFG_SPARTAN3 202 #define CONFIG_FPGA_COUNT 1 203 #define CFG_FPGA_PROG_FEEDBACK 204 #define CFG_FPGA_CHECK_CTRLC 205 */ 206 207 /* Input, PCI, Flexbus, and VCO */ 208 #define CONFIG_EXTRA_CLOCK 209 210 #define CONFIG_PRAM 512 /* 512 KB */ 211 212 #define CFG_PROMPT "-> " 213 #define CFG_LONGHELP /* undef to save memory */ 214 215 #if defined(CONFIG_CMD_KGDB) 216 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 217 #else 218 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 219 #endif 220 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 221 #define CFG_MAXARGS 16 /* max number of command args */ 222 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 223 224 #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000) 225 226 #define CFG_HZ 1000 227 228 #define CFG_MBAR 0xFC000000 229 230 /* 231 * Low Level Configuration Settings 232 * (address mappings, register initial values, etc.) 233 * You should know what you are doing if you make changes here. 234 */ 235 236 /*----------------------------------------------------------------------- 237 * Definitions for initial stack pointer and data area (in DPRAM) 238 */ 239 #define CFG_INIT_RAM_ADDR 0x80000000 240 #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ 241 #define CFG_INIT_RAM_CTRL 0x221 242 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 243 #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16) 244 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 245 246 /*----------------------------------------------------------------------- 247 * Start addresses for the final memory configuration 248 * (Set up by the startup code) 249 * Please note that CFG_SDRAM_BASE _must_ start at 0 250 */ 251 #define CFG_SDRAM_BASE 0x40000000 252 #define CFG_SDRAM_BASE1 0x48000000 253 #define CFG_SDRAM_SIZE 256 /* SDRAM size in MB */ 254 #define CFG_SDRAM_CFG1 0x65311610 255 #define CFG_SDRAM_CFG2 0x59670000 256 #define CFG_SDRAM_CTRL 0xEA0B2000 257 #define CFG_SDRAM_EMOD 0x40010000 258 #define CFG_SDRAM_MODE 0x00010033 259 260 #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 261 #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) 262 263 #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) 264 #define CFG_BOOTPARAMS_LEN 64*1024 265 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 266 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 267 268 /* 269 * For booting Linux, the board info and command line data 270 * have to be in the first 8 MB of memory, since this is 271 * the maximum mapped by the Linux kernel during initialization ?? 272 */ 273 /* Initial Memory map for Linux */ 274 #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) 275 276 /* Configuration for environment 277 * Environment is embedded in u-boot in the second sector of the flash 278 */ 279 #define CFG_ENV_IS_IN_FLASH 1 280 #define CONFIG_ENV_OVERWRITE 1 281 #undef CFG_ENV_IS_EMBEDDED 282 283 /*----------------------------------------------------------------------- 284 * FLASH organization 285 */ 286 #ifdef CFG_ATMEL_BOOT 287 # define CFG_FLASH_BASE CFG_CS0_BASE 288 # define CFG_FLASH0_BASE CFG_CS0_BASE 289 # define CFG_FLASH1_BASE CFG_CS1_BASE 290 # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) 291 # define CFG_ENV_SECT_SIZE 0x2000 292 #else 293 # define CFG_FLASH_BASE CFG_CS0_BASE 294 # define CFG_FLASH0_BASE CFG_CS0_BASE 295 # define CFG_FLASH1_BASE CFG_CS1_BASE 296 # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) 297 # define CFG_ENV_SECT_SIZE 0x20000 298 #endif 299 300 /* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system 301 keep reset. */ 302 #undef CFG_FLASH_CFI 303 #ifdef CFG_FLASH_CFI 304 305 # define CFG_FLASH_CFI_DRIVER 1 306 # define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 307 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT 308 # define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ 309 # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 310 # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 311 # define CFG_FLASH_CHECKSUM 312 # define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE } 313 314 #else 315 316 # define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ 317 318 # define CFG_ATMEL_REGION 4 319 # define CFG_ATMEL_TOTALSECT 11 320 # define CFG_ATMEL_SECT {1, 2, 1, 7} 321 # define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 322 # define CFG_INTEL_SECT 137 323 324 /* max number of sectors on one chip */ 325 # define CFG_MAX_FLASH_SECT (CFG_ATMEL_TOTALSECT + CFG_INTEL_SECT) 326 # define CFG_FLASH_ERASE_TOUT 2000 /* Atmel needs longer timeout */ 327 # define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 328 # define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ 329 # define CFG_FLASH_UNLOCK_TOUT 100 /* Timeout for Flash Clear Lock Bits (in ms) */ 330 # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 331 # define CFG_FLASH_CHECKSUM 332 333 #ifdef CONFIG_SERIAL_FLASH 334 # define CFG_FLASH2_BASE 0x01000000 335 # define CFG_STM_SECT 32 336 # define CFG_STM_SECTSZ 0x10000 337 338 # undef CFG_FLASH_ERASE_TOUT 339 # define CFG_FLASH_ERASE_TOUT 20000 340 341 # define SER_WREN 0x06 342 # define SER_WRDI 0x04 343 # define SER_RDID 0x9F 344 # define SER_RDSR 0x05 345 # define SER_WRSR 0x01 346 # define SER_READ 0x03 347 # define SER_F_READ 0x0B 348 # define SER_PAGE_PROG 0x02 349 # define SER_SECT_ERASE 0xD8 350 # define SER_BULK_ERASE 0xC7 351 # define SER_DEEP_PWRDN 0xB9 352 # define SER_RES 0xAB 353 #endif 354 355 #endif 356 357 /* 358 * This is setting for JFFS2 support in u-boot. 359 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 360 */ 361 #ifdef CFG_ATMEL_BOOT 362 # define CONFIG_JFFS2_DEV "nor1" 363 # define CONFIG_JFFS2_PART_SIZE 0x01000000 364 # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH1_BASE + 0x500000) 365 #else 366 # define CONFIG_JFFS2_DEV "nor0" 367 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 368 # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) 369 #endif 370 371 /*----------------------------------------------------------------------- 372 * Cache Configuration 373 */ 374 #define CFG_CACHELINE_SIZE 16 375 376 /*----------------------------------------------------------------------- 377 * Memory bank definitions 378 */ 379 /* 380 * CS0 - NOR Flash 1, 2, 4, or 8MB 381 * CS1 - CompactFlash and registers 382 * CS2 - CPLD 383 * CS3 - FPGA 384 * CS4 - Available 385 * CS5 - Available 386 */ 387 388 #ifdef CFG_ATMEL_BOOT 389 /* Atmel Flash */ 390 #define CFG_CS0_BASE 0x04000000 391 #define CFG_CS0_MASK 0x00070001 392 #define CFG_CS0_CTRL 0x00001140 393 /* Intel Flash */ 394 #define CFG_CS1_BASE 0x00000000 395 #define CFG_CS1_MASK 0x01FF0001 396 #define CFG_CS1_CTRL 0x00000D60 397 398 #define CFG_ATMEL_BASE CFG_CS0_BASE 399 #else 400 /* Intel Flash */ 401 #define CFG_CS0_BASE 0x00000000 402 #define CFG_CS0_MASK 0x01FF0001 403 #define CFG_CS0_CTRL 0x00000D60 404 /* Atmel Flash */ 405 #define CFG_CS1_BASE 0x04000000 406 #define CFG_CS1_MASK 0x00070001 407 #define CFG_CS1_CTRL 0x00001140 408 409 #define CFG_ATMEL_BASE CFG_CS1_BASE 410 #endif 411 412 /* CPLD */ 413 #define CFG_CS2_BASE 0x08000000 414 #define CFG_CS2_MASK 0x00070001 415 #define CFG_CS2_CTRL 0x003f1140 416 417 /* FPGA */ 418 #define CFG_CS3_BASE 0x09000000 419 #define CFG_CS3_MASK 0x00070001 420 #define CFG_CS3_CTRL 0x00000020 421 422 #endif /* _M54455EVB_H */ 423