1 /* 2 * Configuation settings for the Freescale MCF54455 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef _M54455EVB_H 31 #define _M54455EVB_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_MCF5445x /* define processor family */ 38 #define CONFIG_M54455 /* define processor type */ 39 #define CONFIG_M54455EVB /* M54455EVB board */ 40 41 #define CONFIG_MCFUART 42 #define CFG_UART_PORT (0) 43 #define CONFIG_BAUDRATE 115200 44 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 45 46 #undef CONFIG_WATCHDOG 47 48 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 49 50 /* 51 * BOOTP options 52 */ 53 #define CONFIG_BOOTP_BOOTFILESIZE 54 #define CONFIG_BOOTP_BOOTPATH 55 #define CONFIG_BOOTP_GATEWAY 56 #define CONFIG_BOOTP_HOSTNAME 57 58 /* Command line configuration */ 59 #include <config_cmd_default.h> 60 61 #define CONFIG_CMD_BOOTD 62 #define CONFIG_CMD_CACHE 63 #define CONFIG_CMD_DATE 64 #define CONFIG_CMD_DHCP 65 #define CONFIG_CMD_ELF 66 #define CONFIG_CMD_EXT2 67 #define CONFIG_CMD_FAT 68 #define CONFIG_CMD_FLASH 69 #define CONFIG_CMD_I2C 70 #define CONFIG_CMD_IDE 71 #define CONFIG_CMD_JFFS2 72 #define CONFIG_CMD_MEMORY 73 #define CONFIG_CMD_MISC 74 #define CONFIG_CMD_MII 75 #define CONFIG_CMD_NET 76 #undef CONFIG_CMD_PCI 77 #define CONFIG_CMD_PING 78 #define CONFIG_CMD_REGINFO 79 #define CONFIG_CMD_SPI 80 #define CONFIG_CMD_SF 81 82 #undef CONFIG_CMD_LOADB 83 #undef CONFIG_CMD_LOADS 84 85 /* Network configuration */ 86 #define CONFIG_MCFFEC 87 #ifdef CONFIG_MCFFEC 88 # define CONFIG_NET_MULTI 1 89 # define CONFIG_MII 1 90 # define CONFIG_MII_INIT 1 91 # define CFG_DISCOVER_PHY 92 # define CFG_RX_ETH_BUFFER 8 93 # define CFG_FAULT_ECHO_LINK_DOWN 94 95 # define CFG_FEC0_PINMUX 0 96 # define CFG_FEC1_PINMUX 0 97 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE 98 # define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE 99 # define MCFFEC_TOUT_LOOP 50000 100 # define CONFIG_HAS_ETH1 101 102 # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 103 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" 104 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 105 # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 106 # define CONFIG_ETHPRIME "FEC0" 107 # define CONFIG_IPADDR 192.162.1.2 108 # define CONFIG_NETMASK 255.255.255.0 109 # define CONFIG_SERVERIP 192.162.1.1 110 # define CONFIG_GATEWAYIP 192.162.1.1 111 # define CONFIG_OVERWRITE_ETHADDR_ONCE 112 113 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ 114 # ifndef CFG_DISCOVER_PHY 115 # define FECDUPLEX FULL 116 # define FECSPEED _100BASET 117 # else 118 # ifndef CFG_FAULT_ECHO_LINK_DOWN 119 # define CFG_FAULT_ECHO_LINK_DOWN 120 # endif 121 # endif /* CFG_DISCOVER_PHY */ 122 #endif 123 124 #define CONFIG_HOSTNAME M54455EVB 125 #ifdef CFG_STMICRO_BOOT 126 /* ST Micro serial flash */ 127 #define CFG_LOAD_ADDR2 0x40010013 128 #define CONFIG_EXTRA_ENV_SETTINGS \ 129 "netdev=eth0\0" \ 130 "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ 131 "loadaddr=0x40010000\0" \ 132 "sbfhdr=sbfhdr.bin\0" \ 133 "uboot=u-boot.bin\0" \ 134 "load=tftp ${loadaddr} ${sbfhdr};" \ 135 "tftp " MK_STR(CFG_LOAD_ADDR2) " ${uboot} \0" \ 136 "upd=run load; run prog\0" \ 137 "prog=sf probe 0:1 10000 1;" \ 138 "sf erase 0 30000;" \ 139 "sf write ${loadaddr} 0 0x30000;" \ 140 "save\0" \ 141 "" 142 #else 143 /* Atmel and Intel */ 144 #ifdef CFG_ATMEL_BOOT 145 # define CFG_UBOOT_END 0x0403FFFF 146 #elif defined(CFG_INTEL_BOOT) 147 # define CFG_UBOOT_END 0x3FFFF 148 #endif 149 #define CONFIG_EXTRA_ENV_SETTINGS \ 150 "netdev=eth0\0" \ 151 "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ 152 "loadaddr=0x40010000\0" \ 153 "uboot=u-boot.bin\0" \ 154 "load=tftp ${loadaddr} ${uboot}\0" \ 155 "upd=run load; run prog\0" \ 156 "prog=prot off " MK_STR(CFG_FLASH_BASE) \ 157 " " MK_STR(CFG_UBOOT_END) ";" \ 158 "era " MK_STR(CFG_FLASH_BASE) " " \ 159 MK_STR(CFG_UBOOT_END) ";" \ 160 "cp.b ${loadaddr} " MK_STR(CFG_FLASH_BASE) \ 161 " ${filesize}; save\0" \ 162 "" 163 #endif 164 165 /* ATA configuration */ 166 #define CONFIG_ISO_PARTITION 167 #define CONFIG_DOS_PARTITION 168 #define CONFIG_IDE_RESET 1 169 #define CONFIG_IDE_PREINIT 1 170 #define CONFIG_ATAPI 171 #undef CONFIG_LBA48 172 173 #define CFG_IDE_MAXBUS 1 174 #define CFG_IDE_MAXDEVICE 2 175 176 #define CFG_ATA_BASE_ADDR 0x90000000 177 #define CFG_ATA_IDE0_OFFSET 0 178 179 #define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 180 #define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 181 #define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 182 #define CFG_ATA_STRIDE 4 /* Interval between registers */ 183 #define _IO_BASE 0 184 185 /* Realtime clock */ 186 #define CONFIG_MCFRTC 187 #undef RTC_DEBUG 188 #define CFG_RTC_OSCILLATOR (32 * CFG_HZ) 189 190 /* Timer */ 191 #define CONFIG_MCFTMR 192 #undef CONFIG_MCFPIT 193 194 /* I2c */ 195 #define CONFIG_FSL_I2C 196 #define CONFIG_HARD_I2C /* I2C with hardware support */ 197 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 198 #define CFG_I2C_SPEED 80000 /* I2C speed and slave address */ 199 #define CFG_I2C_SLAVE 0x7F 200 #define CFG_I2C_OFFSET 0x58000 201 #define CFG_IMMR CFG_MBAR 202 203 /* DSPI and Serial Flash */ 204 #define CONFIG_CF_DSPI 205 #define CONFIG_HARD_SPI 206 #define CFG_SER_FLASH_BASE 0x01000000 207 #define CFG_SBFHDR_SIZE 0x13 208 #ifdef CONFIG_CMD_SPI 209 # define CONFIG_SPI_FLASH 210 # define CONFIG_SPI_FLASH_STMICRO 211 212 # define CFG_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ 213 DSPI_DCTAR_CPOL | \ 214 DSPI_DCTAR_CPHA | \ 215 DSPI_DCTAR_PCSSCK_1CLK | \ 216 DSPI_DCTAR_PASC(0) | \ 217 DSPI_DCTAR_PDT(0) | \ 218 DSPI_DCTAR_CSSCK(0) | \ 219 DSPI_DCTAR_ASC(0) | \ 220 DSPI_DCTAR_PBR(0) | \ 221 DSPI_DCTAR_DT(1) | \ 222 DSPI_DCTAR_BR(1)) 223 #endif 224 225 /* PCI */ 226 #ifdef CONFIG_CMD_PCI 227 #define CONFIG_PCI 1 228 #define CONFIG_PCI_PNP 1 229 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 230 231 #define CFG_PCI_CACHE_LINE_SIZE 4 232 233 #define CFG_PCI_MEM_BUS 0xA0000000 234 #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS 235 #define CFG_PCI_MEM_SIZE 0x10000000 236 237 #define CFG_PCI_IO_BUS 0xB1000000 238 #define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS 239 #define CFG_PCI_IO_SIZE 0x01000000 240 241 #define CFG_PCI_CFG_BUS 0xB0000000 242 #define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS 243 #define CFG_PCI_CFG_SIZE 0x01000000 244 #endif 245 246 /* FPGA - Spartan 2 */ 247 /* experiment 248 #define CONFIG_FPGA CFG_SPARTAN3 249 #define CONFIG_FPGA_COUNT 1 250 #define CFG_FPGA_PROG_FEEDBACK 251 #define CFG_FPGA_CHECK_CTRLC 252 */ 253 254 /* Input, PCI, Flexbus, and VCO */ 255 #define CONFIG_EXTRA_CLOCK 256 257 #define CONFIG_PRAM 2048 /* 2048 KB */ 258 259 #define CFG_PROMPT "-> " 260 #define CFG_LONGHELP /* undef to save memory */ 261 262 #if defined(CONFIG_CMD_KGDB) 263 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 264 #else 265 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 266 #endif 267 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 268 #define CFG_MAXARGS 16 /* max number of command args */ 269 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 270 271 #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000) 272 273 #define CFG_HZ 1000 274 275 #define CFG_MBAR 0xFC000000 276 277 /* 278 * Low Level Configuration Settings 279 * (address mappings, register initial values, etc.) 280 * You should know what you are doing if you make changes here. 281 */ 282 283 /*----------------------------------------------------------------------- 284 * Definitions for initial stack pointer and data area (in DPRAM) 285 */ 286 #define CFG_INIT_RAM_ADDR 0x80000000 287 #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ 288 #define CFG_INIT_RAM_CTRL 0x221 289 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 290 #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 32) 291 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 292 #define CFG_SBFHDR_DATA_OFFSET (CFG_INIT_RAM_END - 32) 293 294 /*----------------------------------------------------------------------- 295 * Start addresses for the final memory configuration 296 * (Set up by the startup code) 297 * Please note that CFG_SDRAM_BASE _must_ start at 0 298 */ 299 #define CFG_SDRAM_BASE 0x40000000 300 #define CFG_SDRAM_BASE1 0x48000000 301 #define CFG_SDRAM_SIZE 256 /* SDRAM size in MB */ 302 #define CFG_SDRAM_CFG1 0x65311610 303 #define CFG_SDRAM_CFG2 0x59670000 304 #define CFG_SDRAM_CTRL 0xEA0B2000 305 #define CFG_SDRAM_EMOD 0x40010000 306 #define CFG_SDRAM_MODE 0x00010033 307 #define CFG_SDRAM_DRV_STRENGTH 0xAA 308 309 #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 310 #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) 311 312 #ifdef CONFIG_CF_SBF 313 # define CFG_MONITOR_BASE (TEXT_BASE + 0x400) 314 #else 315 # define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) 316 #endif 317 #define CFG_BOOTPARAMS_LEN 64*1024 318 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 319 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 320 321 /* 322 * For booting Linux, the board info and command line data 323 * have to be in the first 8 MB of memory, since this is 324 * the maximum mapped by the Linux kernel during initialization ?? 325 */ 326 /* Initial Memory map for Linux */ 327 #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) 328 329 /* 330 * Configuration for environment 331 * Environment is embedded in u-boot in the second sector of the flash 332 */ 333 #ifdef CONFIG_CF_SBF 334 # define CONFIG_ENV_IS_IN_SPI_FLASH 335 # define CFG_ENV_SPI_CS 1 336 #else 337 # define CFG_ENV_IS_IN_FLASH 1 338 #endif 339 #undef CONFIG_ENV_OVERWRITE 340 #undef CFG_ENV_IS_EMBEDDED 341 342 /*----------------------------------------------------------------------- 343 * FLASH organization 344 */ 345 #ifdef CFG_STMICRO_BOOT 346 # define CFG_FLASH_BASE CFG_SER_FLASH_BASE 347 # define CFG_FLASH0_BASE CFG_SER_FLASH_BASE 348 # define CFG_FLASH1_BASE CFG_CS0_BASE 349 # define CFG_FLASH2_BASE CFG_CS1_BASE 350 # define CFG_ENV_OFFSET 0x30000 351 # define CFG_ENV_SIZE 0x2000 352 # define CFG_ENV_SECT_SIZE 0x10000 353 #endif 354 #ifdef CFG_ATMEL_BOOT 355 # define CFG_FLASH_BASE CFG_CS0_BASE 356 # define CFG_FLASH0_BASE CFG_CS0_BASE 357 # define CFG_FLASH1_BASE CFG_CS1_BASE 358 # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) 359 # define CFG_ENV_SECT_SIZE 0x2000 360 #endif 361 #ifdef CFG_INTEL_BOOT 362 # define CFG_FLASH_BASE CFG_CS0_BASE 363 # define CFG_FLASH0_BASE CFG_CS0_BASE 364 # define CFG_FLASH1_BASE CFG_CS1_BASE 365 # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) 366 # define CFG_ENV_SIZE 0x2000 367 # define CFG_ENV_SECT_SIZE 0x20000 368 #endif 369 370 #define CFG_FLASH_CFI 371 #ifdef CFG_FLASH_CFI 372 373 # define CONFIG_FLASH_CFI_DRIVER 1 374 # define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 375 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT 376 # define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ 377 # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 378 # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 379 # define CFG_FLASH_CHECKSUM 380 # define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE } 381 # define CONFIG_FLASH_CFI_LEGACY 382 383 #ifdef CONFIG_FLASH_CFI_LEGACY 384 # define CFG_ATMEL_REGION 4 385 # define CFG_ATMEL_TOTALSECT 11 386 # define CFG_ATMEL_SECT {1, 2, 1, 7} 387 # define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 388 #endif 389 #endif 390 391 /* 392 * This is setting for JFFS2 support in u-boot. 393 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 394 */ 395 #ifdef CONFIG_CMD_JFFS2 396 #ifdef CF_STMICRO_BOOT 397 # define CONFIG_JFFS2_DEV "nor1" 398 # define CONFIG_JFFS2_PART_SIZE 0x01000000 399 # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH2_BASE + 0x500000) 400 #endif 401 #ifdef CFG_ATMEL_BOOT 402 # define CONFIG_JFFS2_DEV "nor1" 403 # define CONFIG_JFFS2_PART_SIZE 0x01000000 404 # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH1_BASE + 0x500000) 405 #endif 406 #ifdef CFG_INTEL_BOOT 407 # define CONFIG_JFFS2_DEV "nor0" 408 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 409 # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) 410 #endif 411 #endif 412 413 /*----------------------------------------------------------------------- 414 * Cache Configuration 415 */ 416 #define CFG_CACHELINE_SIZE 16 417 418 /*----------------------------------------------------------------------- 419 * Memory bank definitions 420 */ 421 /* 422 * CS0 - NOR Flash 1, 2, 4, or 8MB 423 * CS1 - CompactFlash and registers 424 * CS2 - CPLD 425 * CS3 - FPGA 426 * CS4 - Available 427 * CS5 - Available 428 */ 429 430 #if defined(CFG_ATMEL_BOOT) || defined(CFG_STMICRO_BOOT) 431 /* Atmel Flash */ 432 #define CFG_CS0_BASE 0x04000000 433 #define CFG_CS0_MASK 0x00070001 434 #define CFG_CS0_CTRL 0x00001140 435 /* Intel Flash */ 436 #define CFG_CS1_BASE 0x00000000 437 #define CFG_CS1_MASK 0x01FF0001 438 #define CFG_CS1_CTRL 0x00000D60 439 440 #define CFG_ATMEL_BASE CFG_CS0_BASE 441 #else 442 /* Intel Flash */ 443 #define CFG_CS0_BASE 0x00000000 444 #define CFG_CS0_MASK 0x01FF0001 445 #define CFG_CS0_CTRL 0x00000D60 446 /* Atmel Flash */ 447 #define CFG_CS1_BASE 0x04000000 448 #define CFG_CS1_MASK 0x00070001 449 #define CFG_CS1_CTRL 0x00001140 450 451 #define CFG_ATMEL_BASE CFG_CS1_BASE 452 #endif 453 454 /* CPLD */ 455 #define CFG_CS2_BASE 0x08000000 456 #define CFG_CS2_MASK 0x00070001 457 #define CFG_CS2_CTRL 0x003f1140 458 459 /* FPGA */ 460 #define CFG_CS3_BASE 0x09000000 461 #define CFG_CS3_MASK 0x00070001 462 #define CFG_CS3_CTRL 0x00000020 463 464 #endif /* _M54455EVB_H */ 465