1 /* 2 * Configuation settings for the Freescale MCF54455 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54455EVB_H 15 #define _M54455EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54455EVB /* M54455EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 26 #undef CONFIG_WATCHDOG 27 28 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 29 30 /* 31 * BOOTP options 32 */ 33 #define CONFIG_BOOTP_BOOTFILESIZE 34 #define CONFIG_BOOTP_BOOTPATH 35 #define CONFIG_BOOTP_GATEWAY 36 #define CONFIG_BOOTP_HOSTNAME 37 38 /* Network configuration */ 39 #define CONFIG_MCFFEC 40 #ifdef CONFIG_MCFFEC 41 # define CONFIG_MII 1 42 # define CONFIG_MII_INIT 1 43 # define CONFIG_SYS_DISCOVER_PHY 44 # define CONFIG_SYS_RX_ETH_BUFFER 8 45 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 46 47 # define CONFIG_SYS_FEC0_PINMUX 0 48 # define CONFIG_SYS_FEC1_PINMUX 0 49 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 50 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 51 # define MCFFEC_TOUT_LOOP 50000 52 # define CONFIG_HAS_ETH1 53 54 # define CONFIG_ETHPRIME "FEC0" 55 # define CONFIG_IPADDR 192.162.1.2 56 # define CONFIG_NETMASK 255.255.255.0 57 # define CONFIG_SERVERIP 192.162.1.1 58 # define CONFIG_GATEWAYIP 192.162.1.1 59 60 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 61 # ifndef CONFIG_SYS_DISCOVER_PHY 62 # define FECDUPLEX FULL 63 # define FECSPEED _100BASET 64 # else 65 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 66 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 67 # endif 68 # endif /* CONFIG_SYS_DISCOVER_PHY */ 69 #endif 70 71 #define CONFIG_HOSTNAME M54455EVB 72 #ifdef CONFIG_SYS_STMICRO_BOOT 73 /* ST Micro serial flash */ 74 #define CONFIG_SYS_LOAD_ADDR2 0x40010013 75 #define CONFIG_EXTRA_ENV_SETTINGS \ 76 "netdev=eth0\0" \ 77 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 78 "loadaddr=0x40010000\0" \ 79 "sbfhdr=sbfhdr.bin\0" \ 80 "uboot=u-boot.bin\0" \ 81 "load=tftp ${loadaddr} ${sbfhdr};" \ 82 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 83 "upd=run load; run prog\0" \ 84 "prog=sf probe 0:1 1000000 3;" \ 85 "sf erase 0 30000;" \ 86 "sf write ${loadaddr} 0 0x30000;" \ 87 "save\0" \ 88 "" 89 #else 90 /* Atmel and Intel */ 91 #ifdef CONFIG_SYS_ATMEL_BOOT 92 # define CONFIG_SYS_UBOOT_END 0x0403FFFF 93 #elif defined(CONFIG_SYS_INTEL_BOOT) 94 # define CONFIG_SYS_UBOOT_END 0x3FFFF 95 #endif 96 #define CONFIG_EXTRA_ENV_SETTINGS \ 97 "netdev=eth0\0" \ 98 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 99 "loadaddr=0x40010000\0" \ 100 "uboot=u-boot.bin\0" \ 101 "load=tftp ${loadaddr} ${uboot}\0" \ 102 "upd=run load; run prog\0" \ 103 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 104 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 105 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 106 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 107 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 108 " ${filesize}; save\0" \ 109 "" 110 #endif 111 112 /* ATA configuration */ 113 #define CONFIG_IDE_RESET 1 114 #define CONFIG_IDE_PREINIT 1 115 #define CONFIG_ATAPI 116 #undef CONFIG_LBA48 117 118 #define CONFIG_SYS_IDE_MAXBUS 1 119 #define CONFIG_SYS_IDE_MAXDEVICE 2 120 121 #define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 122 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 123 124 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 125 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 126 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 127 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 128 129 /* Realtime clock */ 130 #define CONFIG_MCFRTC 131 #undef RTC_DEBUG 132 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 133 134 /* Timer */ 135 #define CONFIG_MCFTMR 136 #undef CONFIG_MCFPIT 137 138 /* I2c */ 139 #define CONFIG_SYS_I2C 140 #define CONFIG_SYS_I2C_FSL 141 #define CONFIG_SYS_FSL_I2C_SPEED 80000 142 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 143 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 144 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 145 146 /* DSPI and Serial Flash */ 147 #define CONFIG_CF_SPI 148 #define CONFIG_CF_DSPI 149 #define CONFIG_HARD_SPI 150 #define CONFIG_SYS_SBFHDR_SIZE 0x13 151 #ifdef CONFIG_CMD_SPI 152 153 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 154 DSPI_CTAR_PCSSCK_1CLK | \ 155 DSPI_CTAR_PASC(0) | \ 156 DSPI_CTAR_PDT(0) | \ 157 DSPI_CTAR_CSSCK(0) | \ 158 DSPI_CTAR_ASC(0) | \ 159 DSPI_CTAR_DT(1)) 160 #endif 161 162 /* PCI */ 163 #ifdef CONFIG_CMD_PCI 164 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 165 166 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 167 168 #define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 169 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 170 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 171 172 #define CONFIG_SYS_PCI_IO_BUS 0xB1000000 173 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 174 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 175 176 #define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 177 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 178 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 179 #endif 180 181 /* FPGA - Spartan 2 */ 182 /* experiment 183 #define CONFIG_FPGA 184 #define CONFIG_FPGA_COUNT 1 185 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 186 #define CONFIG_SYS_FPGA_CHECK_CTRLC 187 */ 188 189 /* Input, PCI, Flexbus, and VCO */ 190 #define CONFIG_EXTRA_CLOCK 191 192 #define CONFIG_PRAM 2048 /* 2048 KB */ 193 194 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 195 196 #if defined(CONFIG_CMD_KGDB) 197 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 198 #else 199 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 200 #endif 201 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 202 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 203 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 204 205 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 206 207 #define CONFIG_SYS_MBAR 0xFC000000 208 209 /* 210 * Low Level Configuration Settings 211 * (address mappings, register initial values, etc.) 212 * You should know what you are doing if you make changes here. 213 */ 214 215 /*----------------------------------------------------------------------- 216 * Definitions for initial stack pointer and data area (in DPRAM) 217 */ 218 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 219 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 220 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 221 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 222 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 223 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 224 225 /*----------------------------------------------------------------------- 226 * Start addresses for the final memory configuration 227 * (Set up by the startup code) 228 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 229 */ 230 #define CONFIG_SYS_SDRAM_BASE 0x40000000 231 #define CONFIG_SYS_SDRAM_BASE1 0x48000000 232 #define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ 233 #define CONFIG_SYS_SDRAM_CFG1 0x65311610 234 #define CONFIG_SYS_SDRAM_CFG2 0x59670000 235 #define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 236 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 237 #define CONFIG_SYS_SDRAM_MODE 0x00010033 238 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA 239 240 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 241 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 242 243 #ifdef CONFIG_CF_SBF 244 # define CONFIG_SERIAL_BOOT 245 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 246 #else 247 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 248 #endif 249 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 250 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 251 252 /* Reserve 256 kB for malloc() */ 253 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 254 255 /* 256 * For booting Linux, the board info and command line data 257 * have to be in the first 8 MB of memory, since this is 258 * the maximum mapped by the Linux kernel during initialization ?? 259 */ 260 /* Initial Memory map for Linux */ 261 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 262 263 /* 264 * Configuration for environment 265 * Environment is not embedded in u-boot. First time runing may have env 266 * crc error warning if there is no correct environment on the flash. 267 */ 268 #ifdef CONFIG_CF_SBF 269 # define CONFIG_ENV_SPI_CS 1 270 #endif 271 #undef CONFIG_ENV_OVERWRITE 272 273 /*----------------------------------------------------------------------- 274 * FLASH organization 275 */ 276 #ifdef CONFIG_SYS_STMICRO_BOOT 277 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 278 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE 279 # define CONFIG_ENV_OFFSET 0x30000 280 # define CONFIG_ENV_SIZE 0x2000 281 # define CONFIG_ENV_SECT_SIZE 0x10000 282 #endif 283 #ifdef CONFIG_SYS_ATMEL_BOOT 284 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 285 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 286 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 287 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 288 # define CONFIG_ENV_SIZE 0x2000 289 # define CONFIG_ENV_SECT_SIZE 0x10000 290 #endif 291 #ifdef CONFIG_SYS_INTEL_BOOT 292 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 293 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 294 # define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 295 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 296 # define CONFIG_ENV_SIZE 0x2000 297 # define CONFIG_ENV_SECT_SIZE 0x20000 298 #endif 299 300 #define CONFIG_SYS_FLASH_CFI 301 #ifdef CONFIG_SYS_FLASH_CFI 302 303 # define CONFIG_FLASH_CFI_DRIVER 1 304 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 305 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 306 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 307 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 308 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 309 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 310 # define CONFIG_SYS_FLASH_CHECKSUM 311 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 312 # define CONFIG_FLASH_CFI_LEGACY 313 314 #ifdef CONFIG_FLASH_CFI_LEGACY 315 # define CONFIG_SYS_ATMEL_REGION 4 316 # define CONFIG_SYS_ATMEL_TOTALSECT 11 317 # define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} 318 # define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 319 #endif 320 #endif 321 322 /* 323 * This is setting for JFFS2 support in u-boot. 324 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 325 */ 326 #ifdef CONFIG_CMD_JFFS2 327 #ifdef CF_STMICRO_BOOT 328 # define CONFIG_JFFS2_DEV "nor1" 329 # define CONFIG_JFFS2_PART_SIZE 0x01000000 330 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) 331 #endif 332 #ifdef CONFIG_SYS_ATMEL_BOOT 333 # define CONFIG_JFFS2_DEV "nor1" 334 # define CONFIG_JFFS2_PART_SIZE 0x01000000 335 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) 336 #endif 337 #ifdef CONFIG_SYS_INTEL_BOOT 338 # define CONFIG_JFFS2_DEV "nor0" 339 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 340 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 341 #endif 342 #endif 343 344 /*----------------------------------------------------------------------- 345 * Cache Configuration 346 */ 347 #define CONFIG_SYS_CACHELINE_SIZE 16 348 349 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 350 CONFIG_SYS_INIT_RAM_SIZE - 8) 351 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 352 CONFIG_SYS_INIT_RAM_SIZE - 4) 353 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 354 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 355 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 356 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 357 CF_ACR_EN | CF_ACR_SM_ALL) 358 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 359 CF_CACR_ICINVA | CF_CACR_EUSP) 360 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 361 CF_CACR_DEC | CF_CACR_DDCM_P | \ 362 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 363 364 /*----------------------------------------------------------------------- 365 * Memory bank definitions 366 */ 367 /* 368 * CS0 - NOR Flash 1, 2, 4, or 8MB 369 * CS1 - CompactFlash and registers 370 * CS2 - CPLD 371 * CS3 - FPGA 372 * CS4 - Available 373 * CS5 - Available 374 */ 375 376 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) 377 /* Atmel Flash */ 378 #define CONFIG_SYS_CS0_BASE 0x04000000 379 #define CONFIG_SYS_CS0_MASK 0x00070001 380 #define CONFIG_SYS_CS0_CTRL 0x00001140 381 /* Intel Flash */ 382 #define CONFIG_SYS_CS1_BASE 0x00000000 383 #define CONFIG_SYS_CS1_MASK 0x01FF0001 384 #define CONFIG_SYS_CS1_CTRL 0x00000D60 385 386 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE 387 #else 388 /* Intel Flash */ 389 #define CONFIG_SYS_CS0_BASE 0x00000000 390 #define CONFIG_SYS_CS0_MASK 0x01FF0001 391 #define CONFIG_SYS_CS0_CTRL 0x00000D60 392 /* Atmel Flash */ 393 #define CONFIG_SYS_CS1_BASE 0x04000000 394 #define CONFIG_SYS_CS1_MASK 0x00070001 395 #define CONFIG_SYS_CS1_CTRL 0x00001140 396 397 #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE 398 #endif 399 400 /* CPLD */ 401 #define CONFIG_SYS_CS2_BASE 0x08000000 402 #define CONFIG_SYS_CS2_MASK 0x00070001 403 #define CONFIG_SYS_CS2_CTRL 0x003f1140 404 405 /* FPGA */ 406 #define CONFIG_SYS_CS3_BASE 0x09000000 407 #define CONFIG_SYS_CS3_MASK 0x00070001 408 #define CONFIG_SYS_CS3_CTRL 0x00000020 409 410 #endif /* _M54455EVB_H */ 411