1 /* 2 * Configuation settings for the Freescale MCF54451 EVB board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54451EVB_H 15 #define _M54451EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54451EVB /* M54451EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 26 #undef CONFIG_WATCHDOG 27 28 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 29 30 /* 31 * BOOTP options 32 */ 33 #define CONFIG_BOOTP_BOOTFILESIZE 34 #define CONFIG_BOOTP_BOOTPATH 35 #define CONFIG_BOOTP_GATEWAY 36 #define CONFIG_BOOTP_HOSTNAME 37 38 /* Command line configuration */ 39 #define CONFIG_CMD_REGINFO 40 41 /* Network configuration */ 42 #define CONFIG_MCFFEC 43 #ifdef CONFIG_MCFFEC 44 # define CONFIG_MII 1 45 # define CONFIG_MII_INIT 1 46 # define CONFIG_SYS_DISCOVER_PHY 47 # define CONFIG_SYS_RX_ETH_BUFFER 8 48 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 49 50 # define CONFIG_SYS_FEC0_PINMUX 0 51 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 52 # define MCFFEC_TOUT_LOOP 50000 53 54 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)" 55 # define CONFIG_ETHPRIME "FEC0" 56 # define CONFIG_IPADDR 192.162.1.2 57 # define CONFIG_NETMASK 255.255.255.0 58 # define CONFIG_SERVERIP 192.162.1.1 59 # define CONFIG_GATEWAYIP 192.162.1.1 60 61 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 62 # ifndef CONFIG_SYS_DISCOVER_PHY 63 # define FECDUPLEX FULL 64 # define FECSPEED _100BASET 65 # else 66 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 67 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 68 # endif 69 # endif /* CONFIG_SYS_DISCOVER_PHY */ 70 #endif 71 72 #define CONFIG_HOSTNAME M54451EVB 73 #ifdef CONFIG_SYS_STMICRO_BOOT 74 /* ST Micro serial flash */ 75 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 76 #define CONFIG_EXTRA_ENV_SETTINGS \ 77 "netdev=eth0\0" \ 78 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 79 "loadaddr=0x40010000\0" \ 80 "sbfhdr=sbfhdr.bin\0" \ 81 "uboot=u-boot.bin\0" \ 82 "load=tftp ${loadaddr} ${sbfhdr};" \ 83 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 84 "upd=run load; run prog\0" \ 85 "prog=sf probe 0:1 1000000 3;" \ 86 "sf erase 0 30000;" \ 87 "sf write ${loadaddr} 0 30000;" \ 88 "save\0" \ 89 "" 90 #else 91 #define CONFIG_SYS_UBOOT_END 0x3FFFF 92 #define CONFIG_EXTRA_ENV_SETTINGS \ 93 "netdev=eth0\0" \ 94 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 95 "loadaddr=40010000\0" \ 96 "u-boot=u-boot.bin\0" \ 97 "load=tftp ${loadaddr) ${u-boot}\0" \ 98 "upd=run load; run prog\0" \ 99 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ 100 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ 101 "cp.b ${loadaddr} 0 ${filesize};" \ 102 "save\0" \ 103 "" 104 #endif 105 106 /* Realtime clock */ 107 #define CONFIG_MCFRTC 108 #undef RTC_DEBUG 109 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 110 111 /* Timer */ 112 #define CONFIG_MCFTMR 113 #undef CONFIG_MCFPIT 114 115 /* I2c */ 116 #define CONFIG_SYS_I2C 117 #define CONFIG_SYS_I2C_FSL 118 #define CONFIG_SYS_FSL_I2C_SPEED 80000 119 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 120 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 121 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 122 123 /* DSPI and Serial Flash */ 124 #define CONFIG_CF_SPI 125 #define CONFIG_CF_DSPI 126 #define CONFIG_SERIAL_FLASH 127 #define CONFIG_HARD_SPI 128 #define CONFIG_SYS_SBFHDR_SIZE 0x7 129 #ifdef CONFIG_CMD_SPI 130 131 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 132 DSPI_CTAR_PCSSCK_1CLK | \ 133 DSPI_CTAR_PASC(0) | \ 134 DSPI_CTAR_PDT(0) | \ 135 DSPI_CTAR_CSSCK(0) | \ 136 DSPI_CTAR_ASC(0) | \ 137 DSPI_CTAR_DT(1)) 138 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 139 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 140 #endif 141 142 /* Input, PCI, Flexbus, and VCO */ 143 #define CONFIG_EXTRA_CLOCK 144 145 #define CONFIG_PRAM 2048 /* 2048 KB */ 146 147 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 148 149 #if defined(CONFIG_CMD_KGDB) 150 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 151 #else 152 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 153 #endif 154 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 155 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 156 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 157 158 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 159 160 #define CONFIG_SYS_MBAR 0xFC000000 161 162 /* 163 * Low Level Configuration Settings 164 * (address mappings, register initial values, etc.) 165 * You should know what you are doing if you make changes here. 166 */ 167 168 /*----------------------------------------------------------------------- 169 * Definitions for initial stack pointer and data area (in DPRAM) 170 */ 171 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 172 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 173 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 174 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 175 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 176 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 177 178 /*----------------------------------------------------------------------- 179 * Start addresses for the final memory configuration 180 * (Set up by the startup code) 181 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 182 */ 183 #define CONFIG_SYS_SDRAM_BASE 0x40000000 184 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 185 #define CONFIG_SYS_SDRAM_CFG1 0x33633F30 186 #define CONFIG_SYS_SDRAM_CFG2 0x57670000 187 #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 188 #define CONFIG_SYS_SDRAM_EMOD 0x80810000 189 #define CONFIG_SYS_SDRAM_MODE 0x008D0000 190 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 191 192 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 193 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 194 195 #ifdef CONFIG_CF_SBF 196 # define CONFIG_SERIAL_BOOT 197 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 198 #else 199 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 200 #endif 201 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 202 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 203 204 /* Reserve 256 kB for malloc() */ 205 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 206 /* 207 * For booting Linux, the board info and command line data 208 * have to be in the first 8 MB of memory, since this is 209 * the maximum mapped by the Linux kernel during initialization ?? 210 */ 211 /* Initial Memory map for Linux */ 212 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 213 214 /* Configuration for environment 215 * Environment is not embedded in u-boot. First time runing may have env 216 * crc error warning if there is no correct environment on the flash. 217 */ 218 #if defined(CONFIG_SYS_STMICRO_BOOT) 219 # define CONFIG_ENV_IS_IN_SPI_FLASH 1 220 # define CONFIG_ENV_SPI_CS 1 221 # define CONFIG_ENV_OFFSET 0x20000 222 # define CONFIG_ENV_SIZE 0x2000 223 # define CONFIG_ENV_SECT_SIZE 0x10000 224 #else 225 # define CONFIG_ENV_IS_IN_FLASH 1 226 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 227 # define CONFIG_ENV_SIZE 0x2000 228 # define CONFIG_ENV_SECT_SIZE 0x20000 229 #endif 230 #undef CONFIG_ENV_OVERWRITE 231 232 /* FLASH organization */ 233 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 234 235 #define CONFIG_SYS_FLASH_CFI 236 #ifdef CONFIG_SYS_FLASH_CFI 237 238 # define CONFIG_FLASH_CFI_DRIVER 1 239 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 240 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 241 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 242 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 243 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 244 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 245 # define CONFIG_SYS_FLASH_CHECKSUM 246 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 247 248 #endif 249 250 /* 251 * This is setting for JFFS2 support in u-boot. 252 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 253 */ 254 #ifdef CONFIG_CMD_JFFS2 255 # define CONFIG_JFFS2_DEV "nor0" 256 # define CONFIG_JFFS2_PART_SIZE 0x01000000 257 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 258 #endif 259 260 /* Cache Configuration */ 261 #define CONFIG_SYS_CACHELINE_SIZE 16 262 263 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 264 CONFIG_SYS_INIT_RAM_SIZE - 8) 265 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 266 CONFIG_SYS_INIT_RAM_SIZE - 4) 267 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 268 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 269 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 270 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 271 CF_ACR_EN | CF_ACR_SM_ALL) 272 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 273 CF_CACR_ICINVA | CF_CACR_EUSP) 274 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 275 CF_CACR_DEC | CF_CACR_DDCM_P | \ 276 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 277 278 /*----------------------------------------------------------------------- 279 * Memory bank definitions 280 */ 281 /* 282 * CS0 - NOR Flash 16MB 283 * CS1 - Available 284 * CS2 - Available 285 * CS3 - Available 286 * CS4 - Available 287 * CS5 - Available 288 */ 289 290 /* Flash */ 291 #define CONFIG_SYS_CS0_BASE 0x00000000 292 #define CONFIG_SYS_CS0_MASK 0x00FF0001 293 #define CONFIG_SYS_CS0_CTRL 0x00004D80 294 295 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE 296 297 #endif /* _M54451EVB_H */ 298