1 /* 2 * Configuation settings for the Freescale MCF54451 EVB board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef _M54451EVB_H 31 #define _M54451EVB_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_MCF5445x /* define processor family */ 38 #define CONFIG_M54451 /* define processor type */ 39 #define CONFIG_M54451EVB /* M54451EVB board */ 40 41 #define CONFIG_MCFUART 42 #define CONFIG_SYS_UART_PORT (0) 43 #define CONFIG_BAUDRATE 115200 44 45 #undef CONFIG_WATCHDOG 46 47 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 48 49 /* 50 * BOOTP options 51 */ 52 #define CONFIG_BOOTP_BOOTFILESIZE 53 #define CONFIG_BOOTP_BOOTPATH 54 #define CONFIG_BOOTP_GATEWAY 55 #define CONFIG_BOOTP_HOSTNAME 56 57 /* Command line configuration */ 58 #include <config_cmd_default.h> 59 60 #define CONFIG_CMD_BOOTD 61 #define CONFIG_CMD_CACHE 62 #define CONFIG_CMD_DATE 63 #define CONFIG_CMD_DHCP 64 #define CONFIG_CMD_ELF 65 #define CONFIG_CMD_FLASH 66 #define CONFIG_CMD_I2C 67 #undef CONFIG_CMD_JFFS2 68 #define CONFIG_CMD_MEMORY 69 #define CONFIG_CMD_MISC 70 #define CONFIG_CMD_MII 71 #define CONFIG_CMD_NET 72 #define CONFIG_CMD_NFS 73 #define CONFIG_CMD_PING 74 #define CONFIG_CMD_REGINFO 75 #define CONFIG_CMD_SPI 76 #define CONFIG_CMD_SF 77 78 #undef CONFIG_CMD_LOADB 79 #undef CONFIG_CMD_LOADS 80 81 /* Network configuration */ 82 #define CONFIG_MCFFEC 83 #ifdef CONFIG_MCFFEC 84 # define CONFIG_MII 1 85 # define CONFIG_MII_INIT 1 86 # define CONFIG_SYS_DISCOVER_PHY 87 # define CONFIG_SYS_RX_ETH_BUFFER 8 88 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 89 90 # define CONFIG_SYS_FEC0_PINMUX 0 91 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 92 # define MCFFEC_TOUT_LOOP 50000 93 94 # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 95 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)" 96 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 97 # define CONFIG_ETHPRIME "FEC0" 98 # define CONFIG_IPADDR 192.162.1.2 99 # define CONFIG_NETMASK 255.255.255.0 100 # define CONFIG_SERVERIP 192.162.1.1 101 # define CONFIG_GATEWAYIP 192.162.1.1 102 # define CONFIG_OVERWRITE_ETHADDR_ONCE 103 104 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 105 # ifndef CONFIG_SYS_DISCOVER_PHY 106 # define FECDUPLEX FULL 107 # define FECSPEED _100BASET 108 # else 109 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 110 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 111 # endif 112 # endif /* CONFIG_SYS_DISCOVER_PHY */ 113 #endif 114 115 #define CONFIG_HOSTNAME M54451EVB 116 #ifdef CONFIG_SYS_STMICRO_BOOT 117 /* ST Micro serial flash */ 118 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 119 #define CONFIG_EXTRA_ENV_SETTINGS \ 120 "netdev=eth0\0" \ 121 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 122 "loadaddr=0x40010000\0" \ 123 "sbfhdr=sbfhdr.bin\0" \ 124 "uboot=u-boot.bin\0" \ 125 "load=tftp ${loadaddr} ${sbfhdr};" \ 126 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 127 "upd=run load; run prog\0" \ 128 "prog=sf probe 0:1 1000000 3;" \ 129 "sf erase 0 30000;" \ 130 "sf write ${loadaddr} 0 30000;" \ 131 "save\0" \ 132 "" 133 #else 134 #define CONFIG_SYS_UBOOT_END 0x3FFFF 135 #define CONFIG_EXTRA_ENV_SETTINGS \ 136 "netdev=eth0\0" \ 137 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 138 "loadaddr=40010000\0" \ 139 "u-boot=u-boot.bin\0" \ 140 "load=tftp ${loadaddr) ${u-boot}\0" \ 141 "upd=run load; run prog\0" \ 142 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ 143 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ 144 "cp.b ${loadaddr} 0 ${filesize};" \ 145 "save\0" \ 146 "" 147 #endif 148 149 /* Realtime clock */ 150 #define CONFIG_MCFRTC 151 #undef RTC_DEBUG 152 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 153 154 /* Timer */ 155 #define CONFIG_MCFTMR 156 #undef CONFIG_MCFPIT 157 158 /* I2c */ 159 #define CONFIG_FSL_I2C 160 #define CONFIG_HARD_I2C /* I2C with hardware support */ 161 #define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */ 162 #define CONFIG_SYS_I2C_SLAVE 0x7F 163 #define CONFIG_SYS_I2C_OFFSET 0x58000 164 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 165 166 /* DSPI and Serial Flash */ 167 #define CONFIG_CF_SPI 168 #define CONFIG_CF_DSPI 169 #define CONFIG_SERIAL_FLASH 170 #define CONFIG_HARD_SPI 171 #define CONFIG_SYS_SBFHDR_SIZE 0x7 172 #ifdef CONFIG_CMD_SPI 173 # define CONFIG_SPI_FLASH 174 # define CONFIG_SPI_FLASH_STMICRO 175 176 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 177 DSPI_CTAR_PCSSCK_1CLK | \ 178 DSPI_CTAR_PASC(0) | \ 179 DSPI_CTAR_PDT(0) | \ 180 DSPI_CTAR_CSSCK(0) | \ 181 DSPI_CTAR_ASC(0) | \ 182 DSPI_CTAR_DT(1)) 183 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 184 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 185 #endif 186 187 /* Input, PCI, Flexbus, and VCO */ 188 #define CONFIG_EXTRA_CLOCK 189 190 #define CONFIG_PRAM 2048 /* 2048 KB */ 191 192 #define CONFIG_SYS_PROMPT "-> " 193 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 194 195 #if defined(CONFIG_CMD_KGDB) 196 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 197 #else 198 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 199 #endif 200 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 201 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 202 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 203 204 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 205 206 #define CONFIG_SYS_HZ 1000 207 208 #define CONFIG_SYS_MBAR 0xFC000000 209 210 /* 211 * Low Level Configuration Settings 212 * (address mappings, register initial values, etc.) 213 * You should know what you are doing if you make changes here. 214 */ 215 216 /*----------------------------------------------------------------------- 217 * Definitions for initial stack pointer and data area (in DPRAM) 218 */ 219 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 220 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 221 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 222 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 223 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 224 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 225 226 /*----------------------------------------------------------------------- 227 * Start addresses for the final memory configuration 228 * (Set up by the startup code) 229 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 230 */ 231 #define CONFIG_SYS_SDRAM_BASE 0x40000000 232 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 233 #define CONFIG_SYS_SDRAM_CFG1 0x33633F30 234 #define CONFIG_SYS_SDRAM_CFG2 0x57670000 235 #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 236 #define CONFIG_SYS_SDRAM_EMOD 0x80810000 237 #define CONFIG_SYS_SDRAM_MODE 0x008D0000 238 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 239 240 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 241 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 242 243 #ifdef CONFIG_CF_SBF 244 # define CONFIG_SERIAL_BOOT 245 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 246 #else 247 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 248 #endif 249 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 250 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 251 252 /* Reserve 256 kB for malloc() */ 253 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 254 /* 255 * For booting Linux, the board info and command line data 256 * have to be in the first 8 MB of memory, since this is 257 * the maximum mapped by the Linux kernel during initialization ?? 258 */ 259 /* Initial Memory map for Linux */ 260 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 261 262 /* Configuration for environment 263 * Environment is not embedded in u-boot. First time runing may have env 264 * crc error warning if there is no correct environment on the flash. 265 */ 266 #if defined(CONFIG_SYS_STMICRO_BOOT) 267 # define CONFIG_ENV_IS_IN_SPI_FLASH 1 268 # define CONFIG_ENV_SPI_CS 1 269 # define CONFIG_ENV_OFFSET 0x20000 270 # define CONFIG_ENV_SIZE 0x2000 271 # define CONFIG_ENV_SECT_SIZE 0x10000 272 #else 273 # define CONFIG_ENV_IS_IN_FLASH 1 274 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 275 # define CONFIG_ENV_SIZE 0x2000 276 # define CONFIG_ENV_SECT_SIZE 0x20000 277 #endif 278 #undef CONFIG_ENV_OVERWRITE 279 280 /* FLASH organization */ 281 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 282 283 #define CONFIG_SYS_FLASH_CFI 284 #ifdef CONFIG_SYS_FLASH_CFI 285 286 # define CONFIG_FLASH_CFI_DRIVER 1 287 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 288 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 289 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 290 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 291 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 292 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 293 # define CONFIG_SYS_FLASH_CHECKSUM 294 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 295 296 #endif 297 298 /* 299 * This is setting for JFFS2 support in u-boot. 300 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 301 */ 302 #ifdef CONFIG_CMD_JFFS2 303 # define CONFIG_JFFS2_DEV "nor0" 304 # define CONFIG_JFFS2_PART_SIZE 0x01000000 305 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 306 #endif 307 308 /* Cache Configuration */ 309 #define CONFIG_SYS_CACHELINE_SIZE 16 310 311 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 312 CONFIG_SYS_INIT_RAM_SIZE - 8) 313 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 314 CONFIG_SYS_INIT_RAM_SIZE - 4) 315 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 316 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 317 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 318 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 319 CF_ACR_EN | CF_ACR_SM_ALL) 320 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 321 CF_CACR_ICINVA | CF_CACR_EUSP) 322 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 323 CF_CACR_DEC | CF_CACR_DDCM_P | \ 324 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 325 326 /*----------------------------------------------------------------------- 327 * Memory bank definitions 328 */ 329 /* 330 * CS0 - NOR Flash 16MB 331 * CS1 - Available 332 * CS2 - Available 333 * CS3 - Available 334 * CS4 - Available 335 * CS5 - Available 336 */ 337 338 /* Flash */ 339 #define CONFIG_SYS_CS0_BASE 0x00000000 340 #define CONFIG_SYS_CS0_MASK 0x00FF0001 341 #define CONFIG_SYS_CS0_CTRL 0x00004D80 342 343 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE 344 345 #endif /* _M54451EVB_H */ 346