1 /* 2 * Configuation settings for the Freescale MCF54451 EVB board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54451EVB_H 15 #define _M54451EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54451EVB /* M54451EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 26 #define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*) 27 28 #undef CONFIG_WATCHDOG 29 30 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 31 32 /* 33 * BOOTP options 34 */ 35 #define CONFIG_BOOTP_BOOTFILESIZE 36 #define CONFIG_BOOTP_BOOTPATH 37 #define CONFIG_BOOTP_GATEWAY 38 #define CONFIG_BOOTP_HOSTNAME 39 40 /* Network configuration */ 41 #define CONFIG_MCFFEC 42 #ifdef CONFIG_MCFFEC 43 # define CONFIG_MII 1 44 # define CONFIG_MII_INIT 1 45 # define CONFIG_SYS_DISCOVER_PHY 46 # define CONFIG_SYS_RX_ETH_BUFFER 8 47 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 48 49 # define CONFIG_SYS_FEC0_PINMUX 0 50 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 51 # define MCFFEC_TOUT_LOOP 50000 52 53 # define CONFIG_ETHPRIME "FEC0" 54 # define CONFIG_IPADDR 192.162.1.2 55 # define CONFIG_NETMASK 255.255.255.0 56 # define CONFIG_SERVERIP 192.162.1.1 57 # define CONFIG_GATEWAYIP 192.162.1.1 58 59 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 60 # ifndef CONFIG_SYS_DISCOVER_PHY 61 # define FECDUPLEX FULL 62 # define FECSPEED _100BASET 63 # else 64 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 65 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 66 # endif 67 # endif /* CONFIG_SYS_DISCOVER_PHY */ 68 #endif 69 70 #define CONFIG_HOSTNAME M54451EVB 71 #ifdef CONFIG_SYS_STMICRO_BOOT 72 /* ST Micro serial flash */ 73 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 74 #define CONFIG_EXTRA_ENV_SETTINGS \ 75 "netdev=eth0\0" \ 76 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 77 "loadaddr=0x40010000\0" \ 78 "sbfhdr=sbfhdr.bin\0" \ 79 "uboot=u-boot.bin\0" \ 80 "load=tftp ${loadaddr} ${sbfhdr};" \ 81 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 82 "upd=run load; run prog\0" \ 83 "prog=sf probe 0:1 1000000 3;" \ 84 "sf erase 0 30000;" \ 85 "sf write ${loadaddr} 0 30000;" \ 86 "save\0" \ 87 "" 88 #else 89 #define CONFIG_SYS_UBOOT_END 0x3FFFF 90 #define CONFIG_EXTRA_ENV_SETTINGS \ 91 "netdev=eth0\0" \ 92 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 93 "loadaddr=40010000\0" \ 94 "u-boot=u-boot.bin\0" \ 95 "load=tftp ${loadaddr) ${u-boot}\0" \ 96 "upd=run load; run prog\0" \ 97 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ 98 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ 99 "cp.b ${loadaddr} 0 ${filesize};" \ 100 "save\0" \ 101 "" 102 #endif 103 104 /* Realtime clock */ 105 #define CONFIG_MCFRTC 106 #undef RTC_DEBUG 107 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 108 109 /* Timer */ 110 #define CONFIG_MCFTMR 111 #undef CONFIG_MCFPIT 112 113 /* I2c */ 114 #define CONFIG_SYS_I2C 115 #define CONFIG_SYS_I2C_FSL 116 #define CONFIG_SYS_FSL_I2C_SPEED 80000 117 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 118 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 119 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 120 121 /* DSPI and Serial Flash */ 122 #define CONFIG_CF_SPI 123 #define CONFIG_CF_DSPI 124 #define CONFIG_SERIAL_FLASH 125 #define CONFIG_HARD_SPI 126 #define CONFIG_SYS_SBFHDR_SIZE 0x7 127 #ifdef CONFIG_CMD_SPI 128 129 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 130 DSPI_CTAR_PCSSCK_1CLK | \ 131 DSPI_CTAR_PASC(0) | \ 132 DSPI_CTAR_PDT(0) | \ 133 DSPI_CTAR_CSSCK(0) | \ 134 DSPI_CTAR_ASC(0) | \ 135 DSPI_CTAR_DT(1)) 136 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 137 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 138 #endif 139 140 /* Input, PCI, Flexbus, and VCO */ 141 #define CONFIG_EXTRA_CLOCK 142 143 #define CONFIG_PRAM 2048 /* 2048 KB */ 144 145 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 146 147 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 148 149 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 150 151 #define CONFIG_SYS_MBAR 0xFC000000 152 153 /* 154 * Low Level Configuration Settings 155 * (address mappings, register initial values, etc.) 156 * You should know what you are doing if you make changes here. 157 */ 158 159 /*----------------------------------------------------------------------- 160 * Definitions for initial stack pointer and data area (in DPRAM) 161 */ 162 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 163 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 164 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 165 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 166 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 167 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 168 169 /*----------------------------------------------------------------------- 170 * Start addresses for the final memory configuration 171 * (Set up by the startup code) 172 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 173 */ 174 #define CONFIG_SYS_SDRAM_BASE 0x40000000 175 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 176 #define CONFIG_SYS_SDRAM_CFG1 0x33633F30 177 #define CONFIG_SYS_SDRAM_CFG2 0x57670000 178 #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 179 #define CONFIG_SYS_SDRAM_EMOD 0x80810000 180 #define CONFIG_SYS_SDRAM_MODE 0x008D0000 181 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 182 183 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 184 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 185 186 #ifdef CONFIG_CF_SBF 187 # define CONFIG_SERIAL_BOOT 188 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 189 #else 190 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 191 #endif 192 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 193 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 194 195 /* Reserve 256 kB for malloc() */ 196 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 197 /* 198 * For booting Linux, the board info and command line data 199 * have to be in the first 8 MB of memory, since this is 200 * the maximum mapped by the Linux kernel during initialization ?? 201 */ 202 /* Initial Memory map for Linux */ 203 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 204 205 /* Configuration for environment 206 * Environment is not embedded in u-boot. First time runing may have env 207 * crc error warning if there is no correct environment on the flash. 208 */ 209 #if defined(CONFIG_SYS_STMICRO_BOOT) 210 # define CONFIG_ENV_SPI_CS 1 211 # define CONFIG_ENV_OFFSET 0x20000 212 # define CONFIG_ENV_SIZE 0x2000 213 # define CONFIG_ENV_SECT_SIZE 0x10000 214 #else 215 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 216 # define CONFIG_ENV_SIZE 0x2000 217 # define CONFIG_ENV_SECT_SIZE 0x20000 218 #endif 219 #undef CONFIG_ENV_OVERWRITE 220 221 /* FLASH organization */ 222 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 223 224 #define CONFIG_SYS_FLASH_CFI 225 #ifdef CONFIG_SYS_FLASH_CFI 226 227 # define CONFIG_FLASH_CFI_DRIVER 1 228 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 229 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 230 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 231 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 232 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 233 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 234 # define CONFIG_SYS_FLASH_CHECKSUM 235 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 236 237 #endif 238 239 /* 240 * This is setting for JFFS2 support in u-boot. 241 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 242 */ 243 #ifdef CONFIG_CMD_JFFS2 244 # define CONFIG_JFFS2_DEV "nor0" 245 # define CONFIG_JFFS2_PART_SIZE 0x01000000 246 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 247 #endif 248 249 /* Cache Configuration */ 250 #define CONFIG_SYS_CACHELINE_SIZE 16 251 252 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 253 CONFIG_SYS_INIT_RAM_SIZE - 8) 254 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 255 CONFIG_SYS_INIT_RAM_SIZE - 4) 256 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 257 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 258 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 259 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 260 CF_ACR_EN | CF_ACR_SM_ALL) 261 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 262 CF_CACR_ICINVA | CF_CACR_EUSP) 263 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 264 CF_CACR_DEC | CF_CACR_DDCM_P | \ 265 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 266 267 /*----------------------------------------------------------------------- 268 * Memory bank definitions 269 */ 270 /* 271 * CS0 - NOR Flash 16MB 272 * CS1 - Available 273 * CS2 - Available 274 * CS3 - Available 275 * CS4 - Available 276 * CS5 - Available 277 */ 278 279 /* Flash */ 280 #define CONFIG_SYS_CS0_BASE 0x00000000 281 #define CONFIG_SYS_CS0_MASK 0x00FF0001 282 #define CONFIG_SYS_CS0_CTRL 0x00004D80 283 284 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE 285 286 #endif /* _M54451EVB_H */ 287