1 /* 2 * Configuation settings for the Freescale MCF54451 EVB board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54451EVB_H 15 #define _M54451EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_MCF5445x /* define processor family */ 22 #define CONFIG_M54451 /* define processor type */ 23 #define CONFIG_M54451EVB /* M54451EVB board */ 24 25 #define CONFIG_DISPLAY_BOARDINFO 26 27 #define CONFIG_MCFUART 28 #define CONFIG_SYS_UART_PORT (0) 29 #define CONFIG_BAUDRATE 115200 30 31 #undef CONFIG_WATCHDOG 32 33 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 34 35 /* 36 * BOOTP options 37 */ 38 #define CONFIG_BOOTP_BOOTFILESIZE 39 #define CONFIG_BOOTP_BOOTPATH 40 #define CONFIG_BOOTP_GATEWAY 41 #define CONFIG_BOOTP_HOSTNAME 42 43 /* Command line configuration */ 44 #include <config_cmd_default.h> 45 46 #define CONFIG_CMD_BOOTD 47 #define CONFIG_CMD_CACHE 48 #define CONFIG_CMD_DATE 49 #define CONFIG_CMD_DHCP 50 #define CONFIG_CMD_ELF 51 #define CONFIG_CMD_FLASH 52 #define CONFIG_CMD_I2C 53 #undef CONFIG_CMD_JFFS2 54 #define CONFIG_CMD_MEMORY 55 #define CONFIG_CMD_MISC 56 #define CONFIG_CMD_MII 57 #define CONFIG_CMD_NET 58 #define CONFIG_CMD_NFS 59 #define CONFIG_CMD_PING 60 #define CONFIG_CMD_REGINFO 61 #define CONFIG_CMD_SPI 62 #define CONFIG_CMD_SF 63 64 #undef CONFIG_CMD_LOADB 65 #undef CONFIG_CMD_LOADS 66 67 /* Network configuration */ 68 #define CONFIG_MCFFEC 69 #ifdef CONFIG_MCFFEC 70 # define CONFIG_MII 1 71 # define CONFIG_MII_INIT 1 72 # define CONFIG_SYS_DISCOVER_PHY 73 # define CONFIG_SYS_RX_ETH_BUFFER 8 74 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 75 76 # define CONFIG_SYS_FEC0_PINMUX 0 77 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 78 # define MCFFEC_TOUT_LOOP 50000 79 80 # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 81 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)" 82 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 83 # define CONFIG_ETHPRIME "FEC0" 84 # define CONFIG_IPADDR 192.162.1.2 85 # define CONFIG_NETMASK 255.255.255.0 86 # define CONFIG_SERVERIP 192.162.1.1 87 # define CONFIG_GATEWAYIP 192.162.1.1 88 # define CONFIG_OVERWRITE_ETHADDR_ONCE 89 90 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 91 # ifndef CONFIG_SYS_DISCOVER_PHY 92 # define FECDUPLEX FULL 93 # define FECSPEED _100BASET 94 # else 95 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 96 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 97 # endif 98 # endif /* CONFIG_SYS_DISCOVER_PHY */ 99 #endif 100 101 #define CONFIG_HOSTNAME M54451EVB 102 #ifdef CONFIG_SYS_STMICRO_BOOT 103 /* ST Micro serial flash */ 104 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 105 #define CONFIG_EXTRA_ENV_SETTINGS \ 106 "netdev=eth0\0" \ 107 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 108 "loadaddr=0x40010000\0" \ 109 "sbfhdr=sbfhdr.bin\0" \ 110 "uboot=u-boot.bin\0" \ 111 "load=tftp ${loadaddr} ${sbfhdr};" \ 112 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 113 "upd=run load; run prog\0" \ 114 "prog=sf probe 0:1 1000000 3;" \ 115 "sf erase 0 30000;" \ 116 "sf write ${loadaddr} 0 30000;" \ 117 "save\0" \ 118 "" 119 #else 120 #define CONFIG_SYS_UBOOT_END 0x3FFFF 121 #define CONFIG_EXTRA_ENV_SETTINGS \ 122 "netdev=eth0\0" \ 123 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 124 "loadaddr=40010000\0" \ 125 "u-boot=u-boot.bin\0" \ 126 "load=tftp ${loadaddr) ${u-boot}\0" \ 127 "upd=run load; run prog\0" \ 128 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ 129 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ 130 "cp.b ${loadaddr} 0 ${filesize};" \ 131 "save\0" \ 132 "" 133 #endif 134 135 /* Realtime clock */ 136 #define CONFIG_MCFRTC 137 #undef RTC_DEBUG 138 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 139 140 /* Timer */ 141 #define CONFIG_MCFTMR 142 #undef CONFIG_MCFPIT 143 144 /* I2c */ 145 #define CONFIG_SYS_I2C 146 #define CONFIG_SYS_I2C_FSL 147 #define CONFIG_SYS_FSL_I2C_SPEED 80000 148 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 149 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 150 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 151 152 /* DSPI and Serial Flash */ 153 #define CONFIG_CF_SPI 154 #define CONFIG_CF_DSPI 155 #define CONFIG_SERIAL_FLASH 156 #define CONFIG_HARD_SPI 157 #define CONFIG_SYS_SBFHDR_SIZE 0x7 158 #ifdef CONFIG_CMD_SPI 159 # define CONFIG_SPI_FLASH 160 # define CONFIG_SPI_FLASH_STMICRO 161 162 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 163 DSPI_CTAR_PCSSCK_1CLK | \ 164 DSPI_CTAR_PASC(0) | \ 165 DSPI_CTAR_PDT(0) | \ 166 DSPI_CTAR_CSSCK(0) | \ 167 DSPI_CTAR_ASC(0) | \ 168 DSPI_CTAR_DT(1)) 169 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 170 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 171 #endif 172 173 /* Input, PCI, Flexbus, and VCO */ 174 #define CONFIG_EXTRA_CLOCK 175 176 #define CONFIG_PRAM 2048 /* 2048 KB */ 177 178 #define CONFIG_SYS_PROMPT "-> " 179 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 180 181 #if defined(CONFIG_CMD_KGDB) 182 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 183 #else 184 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 185 #endif 186 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 187 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 188 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 189 190 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 191 192 #define CONFIG_SYS_MBAR 0xFC000000 193 194 /* 195 * Low Level Configuration Settings 196 * (address mappings, register initial values, etc.) 197 * You should know what you are doing if you make changes here. 198 */ 199 200 /*----------------------------------------------------------------------- 201 * Definitions for initial stack pointer and data area (in DPRAM) 202 */ 203 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 204 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 205 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 206 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 207 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 208 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 209 210 /*----------------------------------------------------------------------- 211 * Start addresses for the final memory configuration 212 * (Set up by the startup code) 213 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 214 */ 215 #define CONFIG_SYS_SDRAM_BASE 0x40000000 216 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 217 #define CONFIG_SYS_SDRAM_CFG1 0x33633F30 218 #define CONFIG_SYS_SDRAM_CFG2 0x57670000 219 #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 220 #define CONFIG_SYS_SDRAM_EMOD 0x80810000 221 #define CONFIG_SYS_SDRAM_MODE 0x008D0000 222 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 223 224 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 225 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 226 227 #ifdef CONFIG_CF_SBF 228 # define CONFIG_SERIAL_BOOT 229 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 230 #else 231 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 232 #endif 233 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 234 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 235 236 /* Reserve 256 kB for malloc() */ 237 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 238 /* 239 * For booting Linux, the board info and command line data 240 * have to be in the first 8 MB of memory, since this is 241 * the maximum mapped by the Linux kernel during initialization ?? 242 */ 243 /* Initial Memory map for Linux */ 244 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 245 246 /* Configuration for environment 247 * Environment is not embedded in u-boot. First time runing may have env 248 * crc error warning if there is no correct environment on the flash. 249 */ 250 #if defined(CONFIG_SYS_STMICRO_BOOT) 251 # define CONFIG_ENV_IS_IN_SPI_FLASH 1 252 # define CONFIG_ENV_SPI_CS 1 253 # define CONFIG_ENV_OFFSET 0x20000 254 # define CONFIG_ENV_SIZE 0x2000 255 # define CONFIG_ENV_SECT_SIZE 0x10000 256 #else 257 # define CONFIG_ENV_IS_IN_FLASH 1 258 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 259 # define CONFIG_ENV_SIZE 0x2000 260 # define CONFIG_ENV_SECT_SIZE 0x20000 261 #endif 262 #undef CONFIG_ENV_OVERWRITE 263 264 /* FLASH organization */ 265 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 266 267 #define CONFIG_SYS_FLASH_CFI 268 #ifdef CONFIG_SYS_FLASH_CFI 269 270 # define CONFIG_FLASH_CFI_DRIVER 1 271 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 272 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 273 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 274 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 275 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 276 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 277 # define CONFIG_SYS_FLASH_CHECKSUM 278 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 279 280 #endif 281 282 /* 283 * This is setting for JFFS2 support in u-boot. 284 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 285 */ 286 #ifdef CONFIG_CMD_JFFS2 287 # define CONFIG_JFFS2_DEV "nor0" 288 # define CONFIG_JFFS2_PART_SIZE 0x01000000 289 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 290 #endif 291 292 /* Cache Configuration */ 293 #define CONFIG_SYS_CACHELINE_SIZE 16 294 295 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 296 CONFIG_SYS_INIT_RAM_SIZE - 8) 297 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 298 CONFIG_SYS_INIT_RAM_SIZE - 4) 299 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 300 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 301 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 302 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 303 CF_ACR_EN | CF_ACR_SM_ALL) 304 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 305 CF_CACR_ICINVA | CF_CACR_EUSP) 306 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 307 CF_CACR_DEC | CF_CACR_DDCM_P | \ 308 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 309 310 /*----------------------------------------------------------------------- 311 * Memory bank definitions 312 */ 313 /* 314 * CS0 - NOR Flash 16MB 315 * CS1 - Available 316 * CS2 - Available 317 * CS3 - Available 318 * CS4 - Available 319 * CS5 - Available 320 */ 321 322 /* Flash */ 323 #define CONFIG_SYS_CS0_BASE 0x00000000 324 #define CONFIG_SYS_CS0_MASK 0x00FF0001 325 #define CONFIG_SYS_CS0_CTRL 0x00004D80 326 327 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE 328 329 #endif /* _M54451EVB_H */ 330