1 /* 2 * Configuation settings for the Freescale MCF54451 EVB board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54451EVB_H 15 #define _M54451EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54451EVB /* M54451EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 26 #define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*) 27 28 #undef CONFIG_WATCHDOG 29 30 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 31 32 /* 33 * BOOTP options 34 */ 35 #define CONFIG_BOOTP_BOOTFILESIZE 36 37 /* Network configuration */ 38 #define CONFIG_MCFFEC 39 #ifdef CONFIG_MCFFEC 40 # define CONFIG_MII 1 41 # define CONFIG_MII_INIT 1 42 # define CONFIG_SYS_DISCOVER_PHY 43 # define CONFIG_SYS_RX_ETH_BUFFER 8 44 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 45 46 # define CONFIG_SYS_FEC0_PINMUX 0 47 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 48 # define MCFFEC_TOUT_LOOP 50000 49 50 # define CONFIG_ETHPRIME "FEC0" 51 # define CONFIG_IPADDR 192.162.1.2 52 # define CONFIG_NETMASK 255.255.255.0 53 # define CONFIG_SERVERIP 192.162.1.1 54 # define CONFIG_GATEWAYIP 192.162.1.1 55 56 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 57 # ifndef CONFIG_SYS_DISCOVER_PHY 58 # define FECDUPLEX FULL 59 # define FECSPEED _100BASET 60 # else 61 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 62 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 63 # endif 64 # endif /* CONFIG_SYS_DISCOVER_PHY */ 65 #endif 66 67 #define CONFIG_HOSTNAME M54451EVB 68 #ifdef CONFIG_SYS_STMICRO_BOOT 69 /* ST Micro serial flash */ 70 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 71 #define CONFIG_EXTRA_ENV_SETTINGS \ 72 "netdev=eth0\0" \ 73 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 74 "loadaddr=0x40010000\0" \ 75 "sbfhdr=sbfhdr.bin\0" \ 76 "uboot=u-boot.bin\0" \ 77 "load=tftp ${loadaddr} ${sbfhdr};" \ 78 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 79 "upd=run load; run prog\0" \ 80 "prog=sf probe 0:1 1000000 3;" \ 81 "sf erase 0 30000;" \ 82 "sf write ${loadaddr} 0 30000;" \ 83 "save\0" \ 84 "" 85 #else 86 #define CONFIG_SYS_UBOOT_END 0x3FFFF 87 #define CONFIG_EXTRA_ENV_SETTINGS \ 88 "netdev=eth0\0" \ 89 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 90 "loadaddr=40010000\0" \ 91 "u-boot=u-boot.bin\0" \ 92 "load=tftp ${loadaddr) ${u-boot}\0" \ 93 "upd=run load; run prog\0" \ 94 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ 95 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ 96 "cp.b ${loadaddr} 0 ${filesize};" \ 97 "save\0" \ 98 "" 99 #endif 100 101 /* Realtime clock */ 102 #define CONFIG_MCFRTC 103 #undef RTC_DEBUG 104 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 105 106 /* Timer */ 107 #define CONFIG_MCFTMR 108 #undef CONFIG_MCFPIT 109 110 /* I2c */ 111 #define CONFIG_SYS_I2C 112 #define CONFIG_SYS_I2C_FSL 113 #define CONFIG_SYS_FSL_I2C_SPEED 80000 114 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 115 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 116 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 117 118 /* DSPI and Serial Flash */ 119 #define CONFIG_CF_DSPI 120 #define CONFIG_SERIAL_FLASH 121 #define CONFIG_HARD_SPI 122 #define CONFIG_SYS_SBFHDR_SIZE 0x7 123 #ifdef CONFIG_CMD_SPI 124 125 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 126 DSPI_CTAR_PCSSCK_1CLK | \ 127 DSPI_CTAR_PASC(0) | \ 128 DSPI_CTAR_PDT(0) | \ 129 DSPI_CTAR_CSSCK(0) | \ 130 DSPI_CTAR_ASC(0) | \ 131 DSPI_CTAR_DT(1)) 132 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 133 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 134 #endif 135 136 /* Input, PCI, Flexbus, and VCO */ 137 #define CONFIG_EXTRA_CLOCK 138 139 #define CONFIG_PRAM 2048 /* 2048 KB */ 140 141 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 142 143 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 144 145 #define CONFIG_SYS_MBAR 0xFC000000 146 147 /* 148 * Low Level Configuration Settings 149 * (address mappings, register initial values, etc.) 150 * You should know what you are doing if you make changes here. 151 */ 152 153 /*----------------------------------------------------------------------- 154 * Definitions for initial stack pointer and data area (in DPRAM) 155 */ 156 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 157 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 158 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 159 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 160 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 161 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 162 163 /*----------------------------------------------------------------------- 164 * Start addresses for the final memory configuration 165 * (Set up by the startup code) 166 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 167 */ 168 #define CONFIG_SYS_SDRAM_BASE 0x40000000 169 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 170 #define CONFIG_SYS_SDRAM_CFG1 0x33633F30 171 #define CONFIG_SYS_SDRAM_CFG2 0x57670000 172 #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 173 #define CONFIG_SYS_SDRAM_EMOD 0x80810000 174 #define CONFIG_SYS_SDRAM_MODE 0x008D0000 175 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 176 177 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 178 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 179 180 #ifdef CONFIG_CF_SBF 181 # define CONFIG_SERIAL_BOOT 182 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 183 #else 184 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 185 #endif 186 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 187 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 188 189 /* Reserve 256 kB for malloc() */ 190 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 191 /* 192 * For booting Linux, the board info and command line data 193 * have to be in the first 8 MB of memory, since this is 194 * the maximum mapped by the Linux kernel during initialization ?? 195 */ 196 /* Initial Memory map for Linux */ 197 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 198 199 /* Configuration for environment 200 * Environment is not embedded in u-boot. First time runing may have env 201 * crc error warning if there is no correct environment on the flash. 202 */ 203 #if defined(CONFIG_SYS_STMICRO_BOOT) 204 # define CONFIG_ENV_SPI_CS 1 205 # define CONFIG_ENV_OFFSET 0x20000 206 # define CONFIG_ENV_SIZE 0x2000 207 # define CONFIG_ENV_SECT_SIZE 0x10000 208 #else 209 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 210 # define CONFIG_ENV_SIZE 0x2000 211 # define CONFIG_ENV_SECT_SIZE 0x20000 212 #endif 213 #undef CONFIG_ENV_OVERWRITE 214 215 /* FLASH organization */ 216 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 217 218 #define CONFIG_SYS_FLASH_CFI 219 #ifdef CONFIG_SYS_FLASH_CFI 220 221 # define CONFIG_FLASH_CFI_DRIVER 1 222 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 223 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 224 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 225 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 226 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 227 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 228 # define CONFIG_SYS_FLASH_CHECKSUM 229 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 230 231 #endif 232 233 /* 234 * This is setting for JFFS2 support in u-boot. 235 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 236 */ 237 #ifdef CONFIG_CMD_JFFS2 238 # define CONFIG_JFFS2_DEV "nor0" 239 # define CONFIG_JFFS2_PART_SIZE 0x01000000 240 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 241 #endif 242 243 /* Cache Configuration */ 244 #define CONFIG_SYS_CACHELINE_SIZE 16 245 246 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 247 CONFIG_SYS_INIT_RAM_SIZE - 8) 248 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 249 CONFIG_SYS_INIT_RAM_SIZE - 4) 250 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 251 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 252 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 253 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 254 CF_ACR_EN | CF_ACR_SM_ALL) 255 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 256 CF_CACR_ICINVA | CF_CACR_EUSP) 257 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 258 CF_CACR_DEC | CF_CACR_DDCM_P | \ 259 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 260 261 /*----------------------------------------------------------------------- 262 * Memory bank definitions 263 */ 264 /* 265 * CS0 - NOR Flash 16MB 266 * CS1 - Available 267 * CS2 - Available 268 * CS3 - Available 269 * CS4 - Available 270 * CS5 - Available 271 */ 272 273 /* Flash */ 274 #define CONFIG_SYS_CS0_BASE 0x00000000 275 #define CONFIG_SYS_CS0_MASK 0x00FF0001 276 #define CONFIG_SYS_CS0_CTRL 0x00004D80 277 278 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE 279 280 #endif /* _M54451EVB_H */ 281