1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Freescale MCF54451 EVB board. 4 * 5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M54451EVB_H 14 #define _M54451EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 #define CONFIG_M54451EVB /* M54451EVB board */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*) 26 27 #undef CONFIG_WATCHDOG 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 36 /* Network configuration */ 37 #define CONFIG_MCFFEC 38 #ifdef CONFIG_MCFFEC 39 # define CONFIG_MII_INIT 1 40 # define CONFIG_SYS_DISCOVER_PHY 41 # define CONFIG_SYS_RX_ETH_BUFFER 8 42 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 43 44 # define CONFIG_SYS_FEC0_PINMUX 0 45 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 46 # define MCFFEC_TOUT_LOOP 50000 47 48 # define CONFIG_ETHPRIME "FEC0" 49 # define CONFIG_IPADDR 192.162.1.2 50 # define CONFIG_NETMASK 255.255.255.0 51 # define CONFIG_SERVERIP 192.162.1.1 52 # define CONFIG_GATEWAYIP 192.162.1.1 53 54 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 55 # ifndef CONFIG_SYS_DISCOVER_PHY 56 # define FECDUPLEX FULL 57 # define FECSPEED _100BASET 58 # else 59 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 60 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 61 # endif 62 # endif /* CONFIG_SYS_DISCOVER_PHY */ 63 #endif 64 65 #define CONFIG_HOSTNAME "M54451EVB" 66 #ifdef CONFIG_SYS_STMICRO_BOOT 67 /* ST Micro serial flash */ 68 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 69 #define CONFIG_EXTRA_ENV_SETTINGS \ 70 "netdev=eth0\0" \ 71 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 72 "loadaddr=0x40010000\0" \ 73 "sbfhdr=sbfhdr.bin\0" \ 74 "uboot=u-boot.bin\0" \ 75 "load=tftp ${loadaddr} ${sbfhdr};" \ 76 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 77 "upd=run load; run prog\0" \ 78 "prog=sf probe 0:1 1000000 3;" \ 79 "sf erase 0 30000;" \ 80 "sf write ${loadaddr} 0 30000;" \ 81 "save\0" \ 82 "" 83 #else 84 #define CONFIG_SYS_UBOOT_END 0x3FFFF 85 #define CONFIG_EXTRA_ENV_SETTINGS \ 86 "netdev=eth0\0" \ 87 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 88 "loadaddr=40010000\0" \ 89 "u-boot=u-boot.bin\0" \ 90 "load=tftp ${loadaddr) ${u-boot}\0" \ 91 "upd=run load; run prog\0" \ 92 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ 93 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ 94 "cp.b ${loadaddr} 0 ${filesize};" \ 95 "save\0" \ 96 "" 97 #endif 98 99 /* Realtime clock */ 100 #define CONFIG_MCFRTC 101 #undef RTC_DEBUG 102 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 103 104 /* Timer */ 105 #define CONFIG_MCFTMR 106 #undef CONFIG_MCFPIT 107 108 /* I2c */ 109 #define CONFIG_SYS_I2C 110 #define CONFIG_SYS_I2C_FSL 111 #define CONFIG_SYS_FSL_I2C_SPEED 80000 112 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 113 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 114 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 115 116 /* DSPI and Serial Flash */ 117 #define CONFIG_CF_DSPI 118 #define CONFIG_SERIAL_FLASH 119 #define CONFIG_SYS_SBFHDR_SIZE 0x7 120 #ifdef CONFIG_CMD_SPI 121 122 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 123 DSPI_CTAR_PCSSCK_1CLK | \ 124 DSPI_CTAR_PASC(0) | \ 125 DSPI_CTAR_PDT(0) | \ 126 DSPI_CTAR_CSSCK(0) | \ 127 DSPI_CTAR_ASC(0) | \ 128 DSPI_CTAR_DT(1)) 129 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 130 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 131 #endif 132 133 /* Input, PCI, Flexbus, and VCO */ 134 #define CONFIG_EXTRA_CLOCK 135 136 #define CONFIG_PRAM 2048 /* 2048 KB */ 137 138 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 139 140 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 141 142 #define CONFIG_SYS_MBAR 0xFC000000 143 144 /* 145 * Low Level Configuration Settings 146 * (address mappings, register initial values, etc.) 147 * You should know what you are doing if you make changes here. 148 */ 149 150 /*----------------------------------------------------------------------- 151 * Definitions for initial stack pointer and data area (in DPRAM) 152 */ 153 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 154 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 155 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 156 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 157 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 158 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 159 160 /*----------------------------------------------------------------------- 161 * Start addresses for the final memory configuration 162 * (Set up by the startup code) 163 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 164 */ 165 #define CONFIG_SYS_SDRAM_BASE 0x40000000 166 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 167 #define CONFIG_SYS_SDRAM_CFG1 0x33633F30 168 #define CONFIG_SYS_SDRAM_CFG2 0x57670000 169 #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 170 #define CONFIG_SYS_SDRAM_EMOD 0x80810000 171 #define CONFIG_SYS_SDRAM_MODE 0x008D0000 172 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 173 174 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 175 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 176 177 #ifdef CONFIG_CF_SBF 178 # define CONFIG_SERIAL_BOOT 179 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 180 #else 181 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 182 #endif 183 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 184 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 185 186 /* Reserve 256 kB for malloc() */ 187 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 188 /* 189 * For booting Linux, the board info and command line data 190 * have to be in the first 8 MB of memory, since this is 191 * the maximum mapped by the Linux kernel during initialization ?? 192 */ 193 /* Initial Memory map for Linux */ 194 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 195 196 /* Configuration for environment 197 * Environment is not embedded in u-boot. First time runing may have env 198 * crc error warning if there is no correct environment on the flash. 199 */ 200 #if defined(CONFIG_SYS_STMICRO_BOOT) 201 # define CONFIG_ENV_SPI_CS 1 202 # define CONFIG_ENV_OFFSET 0x20000 203 # define CONFIG_ENV_SIZE 0x2000 204 # define CONFIG_ENV_SECT_SIZE 0x10000 205 #else 206 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 207 # define CONFIG_ENV_SIZE 0x2000 208 # define CONFIG_ENV_SECT_SIZE 0x20000 209 #endif 210 #undef CONFIG_ENV_OVERWRITE 211 212 /* FLASH organization */ 213 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 214 215 #ifdef CONFIG_SYS_FLASH_CFI 216 217 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 218 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 219 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 220 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 221 # define CONFIG_SYS_FLASH_CHECKSUM 222 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 223 224 #endif 225 226 /* 227 * This is setting for JFFS2 support in u-boot. 228 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 229 */ 230 #ifdef CONFIG_CMD_JFFS2 231 # define CONFIG_JFFS2_DEV "nor0" 232 # define CONFIG_JFFS2_PART_SIZE 0x01000000 233 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 234 #endif 235 236 /* Cache Configuration */ 237 #define CONFIG_SYS_CACHELINE_SIZE 16 238 239 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 240 CONFIG_SYS_INIT_RAM_SIZE - 8) 241 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 242 CONFIG_SYS_INIT_RAM_SIZE - 4) 243 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 244 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 245 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 246 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 247 CF_ACR_EN | CF_ACR_SM_ALL) 248 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 249 CF_CACR_ICINVA | CF_CACR_EUSP) 250 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 251 CF_CACR_DEC | CF_CACR_DDCM_P | \ 252 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 253 254 /*----------------------------------------------------------------------- 255 * Memory bank definitions 256 */ 257 /* 258 * CS0 - NOR Flash 16MB 259 * CS1 - Available 260 * CS2 - Available 261 * CS3 - Available 262 * CS4 - Available 263 * CS5 - Available 264 */ 265 266 /* Flash */ 267 #define CONFIG_SYS_CS0_BASE 0x00000000 268 #define CONFIG_SYS_CS0_MASK 0x00FF0001 269 #define CONFIG_SYS_CS0_CTRL 0x00004D80 270 271 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE 272 273 #endif /* _M54451EVB_H */ 274