1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Freescale MCF54451 EVB board. 4 * 5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M54451EVB_H 14 #define _M54451EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 #define CONFIG_M54451EVB /* M54451EVB board */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*) 26 27 #undef CONFIG_WATCHDOG 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 36 /* Network configuration */ 37 #define CONFIG_MCFFEC 38 #ifdef CONFIG_MCFFEC 39 # define CONFIG_MII 1 40 # define CONFIG_MII_INIT 1 41 # define CONFIG_SYS_DISCOVER_PHY 42 # define CONFIG_SYS_RX_ETH_BUFFER 8 43 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 44 45 # define CONFIG_SYS_FEC0_PINMUX 0 46 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 47 # define MCFFEC_TOUT_LOOP 50000 48 49 # define CONFIG_ETHPRIME "FEC0" 50 # define CONFIG_IPADDR 192.162.1.2 51 # define CONFIG_NETMASK 255.255.255.0 52 # define CONFIG_SERVERIP 192.162.1.1 53 # define CONFIG_GATEWAYIP 192.162.1.1 54 55 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 56 # ifndef CONFIG_SYS_DISCOVER_PHY 57 # define FECDUPLEX FULL 58 # define FECSPEED _100BASET 59 # else 60 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 61 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 62 # endif 63 # endif /* CONFIG_SYS_DISCOVER_PHY */ 64 #endif 65 66 #define CONFIG_HOSTNAME "M54451EVB" 67 #ifdef CONFIG_SYS_STMICRO_BOOT 68 /* ST Micro serial flash */ 69 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 70 #define CONFIG_EXTRA_ENV_SETTINGS \ 71 "netdev=eth0\0" \ 72 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 73 "loadaddr=0x40010000\0" \ 74 "sbfhdr=sbfhdr.bin\0" \ 75 "uboot=u-boot.bin\0" \ 76 "load=tftp ${loadaddr} ${sbfhdr};" \ 77 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 78 "upd=run load; run prog\0" \ 79 "prog=sf probe 0:1 1000000 3;" \ 80 "sf erase 0 30000;" \ 81 "sf write ${loadaddr} 0 30000;" \ 82 "save\0" \ 83 "" 84 #else 85 #define CONFIG_SYS_UBOOT_END 0x3FFFF 86 #define CONFIG_EXTRA_ENV_SETTINGS \ 87 "netdev=eth0\0" \ 88 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 89 "loadaddr=40010000\0" \ 90 "u-boot=u-boot.bin\0" \ 91 "load=tftp ${loadaddr) ${u-boot}\0" \ 92 "upd=run load; run prog\0" \ 93 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ 94 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ 95 "cp.b ${loadaddr} 0 ${filesize};" \ 96 "save\0" \ 97 "" 98 #endif 99 100 /* Realtime clock */ 101 #define CONFIG_MCFRTC 102 #undef RTC_DEBUG 103 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 104 105 /* Timer */ 106 #define CONFIG_MCFTMR 107 #undef CONFIG_MCFPIT 108 109 /* I2c */ 110 #define CONFIG_SYS_I2C 111 #define CONFIG_SYS_I2C_FSL 112 #define CONFIG_SYS_FSL_I2C_SPEED 80000 113 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 114 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 115 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 116 117 /* DSPI and Serial Flash */ 118 #define CONFIG_CF_DSPI 119 #define CONFIG_SERIAL_FLASH 120 #define CONFIG_HARD_SPI 121 #define CONFIG_SYS_SBFHDR_SIZE 0x7 122 #ifdef CONFIG_CMD_SPI 123 124 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 125 DSPI_CTAR_PCSSCK_1CLK | \ 126 DSPI_CTAR_PASC(0) | \ 127 DSPI_CTAR_PDT(0) | \ 128 DSPI_CTAR_CSSCK(0) | \ 129 DSPI_CTAR_ASC(0) | \ 130 DSPI_CTAR_DT(1)) 131 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 132 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 133 #endif 134 135 /* Input, PCI, Flexbus, and VCO */ 136 #define CONFIG_EXTRA_CLOCK 137 138 #define CONFIG_PRAM 2048 /* 2048 KB */ 139 140 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 141 142 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 143 144 #define CONFIG_SYS_MBAR 0xFC000000 145 146 /* 147 * Low Level Configuration Settings 148 * (address mappings, register initial values, etc.) 149 * You should know what you are doing if you make changes here. 150 */ 151 152 /*----------------------------------------------------------------------- 153 * Definitions for initial stack pointer and data area (in DPRAM) 154 */ 155 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 156 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 157 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 158 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 159 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 160 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 161 162 /*----------------------------------------------------------------------- 163 * Start addresses for the final memory configuration 164 * (Set up by the startup code) 165 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 166 */ 167 #define CONFIG_SYS_SDRAM_BASE 0x40000000 168 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 169 #define CONFIG_SYS_SDRAM_CFG1 0x33633F30 170 #define CONFIG_SYS_SDRAM_CFG2 0x57670000 171 #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 172 #define CONFIG_SYS_SDRAM_EMOD 0x80810000 173 #define CONFIG_SYS_SDRAM_MODE 0x008D0000 174 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 175 176 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 177 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 178 179 #ifdef CONFIG_CF_SBF 180 # define CONFIG_SERIAL_BOOT 181 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 182 #else 183 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 184 #endif 185 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 186 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 187 188 /* Reserve 256 kB for malloc() */ 189 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 190 /* 191 * For booting Linux, the board info and command line data 192 * have to be in the first 8 MB of memory, since this is 193 * the maximum mapped by the Linux kernel during initialization ?? 194 */ 195 /* Initial Memory map for Linux */ 196 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 197 198 /* Configuration for environment 199 * Environment is not embedded in u-boot. First time runing may have env 200 * crc error warning if there is no correct environment on the flash. 201 */ 202 #if defined(CONFIG_SYS_STMICRO_BOOT) 203 # define CONFIG_ENV_SPI_CS 1 204 # define CONFIG_ENV_OFFSET 0x20000 205 # define CONFIG_ENV_SIZE 0x2000 206 # define CONFIG_ENV_SECT_SIZE 0x10000 207 #else 208 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 209 # define CONFIG_ENV_SIZE 0x2000 210 # define CONFIG_ENV_SECT_SIZE 0x20000 211 #endif 212 #undef CONFIG_ENV_OVERWRITE 213 214 /* FLASH organization */ 215 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 216 217 #define CONFIG_SYS_FLASH_CFI 218 #ifdef CONFIG_SYS_FLASH_CFI 219 220 # define CONFIG_FLASH_CFI_DRIVER 1 221 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 222 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 223 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 224 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 225 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 226 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 227 # define CONFIG_SYS_FLASH_CHECKSUM 228 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 229 230 #endif 231 232 /* 233 * This is setting for JFFS2 support in u-boot. 234 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 235 */ 236 #ifdef CONFIG_CMD_JFFS2 237 # define CONFIG_JFFS2_DEV "nor0" 238 # define CONFIG_JFFS2_PART_SIZE 0x01000000 239 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 240 #endif 241 242 /* Cache Configuration */ 243 #define CONFIG_SYS_CACHELINE_SIZE 16 244 245 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 246 CONFIG_SYS_INIT_RAM_SIZE - 8) 247 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 248 CONFIG_SYS_INIT_RAM_SIZE - 4) 249 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 250 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 251 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 252 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 253 CF_ACR_EN | CF_ACR_SM_ALL) 254 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 255 CF_CACR_ICINVA | CF_CACR_EUSP) 256 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 257 CF_CACR_DEC | CF_CACR_DDCM_P | \ 258 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 259 260 /*----------------------------------------------------------------------- 261 * Memory bank definitions 262 */ 263 /* 264 * CS0 - NOR Flash 16MB 265 * CS1 - Available 266 * CS2 - Available 267 * CS3 - Available 268 * CS4 - Available 269 * CS5 - Available 270 */ 271 272 /* Flash */ 273 #define CONFIG_SYS_CS0_BASE 0x00000000 274 #define CONFIG_SYS_CS0_MASK 0x00FF0001 275 #define CONFIG_SYS_CS0_CTRL 0x00004D80 276 277 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE 278 279 #endif /* _M54451EVB_H */ 280