1 /* 2 * Configuation settings for the Freescale MCF54451 EVB board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54451EVB_H 15 #define _M54451EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54451EVB /* M54451EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 #define CONFIG_BAUDRATE 115200 26 27 #undef CONFIG_WATCHDOG 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 #define CONFIG_BOOTP_BOOTPATH 36 #define CONFIG_BOOTP_GATEWAY 37 #define CONFIG_BOOTP_HOSTNAME 38 39 /* Command line configuration */ 40 #define CONFIG_CMD_DATE 41 #undef CONFIG_CMD_JFFS2 42 #define CONFIG_CMD_REGINFO 43 44 /* Network configuration */ 45 #define CONFIG_MCFFEC 46 #ifdef CONFIG_MCFFEC 47 # define CONFIG_MII 1 48 # define CONFIG_MII_INIT 1 49 # define CONFIG_SYS_DISCOVER_PHY 50 # define CONFIG_SYS_RX_ETH_BUFFER 8 51 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 52 53 # define CONFIG_SYS_FEC0_PINMUX 0 54 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 55 # define MCFFEC_TOUT_LOOP 50000 56 57 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)" 58 # define CONFIG_ETHPRIME "FEC0" 59 # define CONFIG_IPADDR 192.162.1.2 60 # define CONFIG_NETMASK 255.255.255.0 61 # define CONFIG_SERVERIP 192.162.1.1 62 # define CONFIG_GATEWAYIP 192.162.1.1 63 64 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 65 # ifndef CONFIG_SYS_DISCOVER_PHY 66 # define FECDUPLEX FULL 67 # define FECSPEED _100BASET 68 # else 69 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 70 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 71 # endif 72 # endif /* CONFIG_SYS_DISCOVER_PHY */ 73 #endif 74 75 #define CONFIG_HOSTNAME M54451EVB 76 #ifdef CONFIG_SYS_STMICRO_BOOT 77 /* ST Micro serial flash */ 78 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 79 #define CONFIG_EXTRA_ENV_SETTINGS \ 80 "netdev=eth0\0" \ 81 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 82 "loadaddr=0x40010000\0" \ 83 "sbfhdr=sbfhdr.bin\0" \ 84 "uboot=u-boot.bin\0" \ 85 "load=tftp ${loadaddr} ${sbfhdr};" \ 86 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 87 "upd=run load; run prog\0" \ 88 "prog=sf probe 0:1 1000000 3;" \ 89 "sf erase 0 30000;" \ 90 "sf write ${loadaddr} 0 30000;" \ 91 "save\0" \ 92 "" 93 #else 94 #define CONFIG_SYS_UBOOT_END 0x3FFFF 95 #define CONFIG_EXTRA_ENV_SETTINGS \ 96 "netdev=eth0\0" \ 97 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 98 "loadaddr=40010000\0" \ 99 "u-boot=u-boot.bin\0" \ 100 "load=tftp ${loadaddr) ${u-boot}\0" \ 101 "upd=run load; run prog\0" \ 102 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ 103 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ 104 "cp.b ${loadaddr} 0 ${filesize};" \ 105 "save\0" \ 106 "" 107 #endif 108 109 /* Realtime clock */ 110 #define CONFIG_MCFRTC 111 #undef RTC_DEBUG 112 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 113 114 /* Timer */ 115 #define CONFIG_MCFTMR 116 #undef CONFIG_MCFPIT 117 118 /* I2c */ 119 #define CONFIG_SYS_I2C 120 #define CONFIG_SYS_I2C_FSL 121 #define CONFIG_SYS_FSL_I2C_SPEED 80000 122 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 123 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 124 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 125 126 /* DSPI and Serial Flash */ 127 #define CONFIG_CF_SPI 128 #define CONFIG_CF_DSPI 129 #define CONFIG_SERIAL_FLASH 130 #define CONFIG_HARD_SPI 131 #define CONFIG_SYS_SBFHDR_SIZE 0x7 132 #ifdef CONFIG_CMD_SPI 133 134 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 135 DSPI_CTAR_PCSSCK_1CLK | \ 136 DSPI_CTAR_PASC(0) | \ 137 DSPI_CTAR_PDT(0) | \ 138 DSPI_CTAR_CSSCK(0) | \ 139 DSPI_CTAR_ASC(0) | \ 140 DSPI_CTAR_DT(1)) 141 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 142 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 143 #endif 144 145 /* Input, PCI, Flexbus, and VCO */ 146 #define CONFIG_EXTRA_CLOCK 147 148 #define CONFIG_PRAM 2048 /* 2048 KB */ 149 150 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 151 152 #if defined(CONFIG_CMD_KGDB) 153 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 154 #else 155 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 156 #endif 157 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 158 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 159 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 160 161 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 162 163 #define CONFIG_SYS_MBAR 0xFC000000 164 165 /* 166 * Low Level Configuration Settings 167 * (address mappings, register initial values, etc.) 168 * You should know what you are doing if you make changes here. 169 */ 170 171 /*----------------------------------------------------------------------- 172 * Definitions for initial stack pointer and data area (in DPRAM) 173 */ 174 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 175 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 176 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 177 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 178 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 179 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 180 181 /*----------------------------------------------------------------------- 182 * Start addresses for the final memory configuration 183 * (Set up by the startup code) 184 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 185 */ 186 #define CONFIG_SYS_SDRAM_BASE 0x40000000 187 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 188 #define CONFIG_SYS_SDRAM_CFG1 0x33633F30 189 #define CONFIG_SYS_SDRAM_CFG2 0x57670000 190 #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 191 #define CONFIG_SYS_SDRAM_EMOD 0x80810000 192 #define CONFIG_SYS_SDRAM_MODE 0x008D0000 193 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 194 195 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 196 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 197 198 #ifdef CONFIG_CF_SBF 199 # define CONFIG_SERIAL_BOOT 200 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 201 #else 202 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 203 #endif 204 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 205 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 206 207 /* Reserve 256 kB for malloc() */ 208 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 209 /* 210 * For booting Linux, the board info and command line data 211 * have to be in the first 8 MB of memory, since this is 212 * the maximum mapped by the Linux kernel during initialization ?? 213 */ 214 /* Initial Memory map for Linux */ 215 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 216 217 /* Configuration for environment 218 * Environment is not embedded in u-boot. First time runing may have env 219 * crc error warning if there is no correct environment on the flash. 220 */ 221 #if defined(CONFIG_SYS_STMICRO_BOOT) 222 # define CONFIG_ENV_IS_IN_SPI_FLASH 1 223 # define CONFIG_ENV_SPI_CS 1 224 # define CONFIG_ENV_OFFSET 0x20000 225 # define CONFIG_ENV_SIZE 0x2000 226 # define CONFIG_ENV_SECT_SIZE 0x10000 227 #else 228 # define CONFIG_ENV_IS_IN_FLASH 1 229 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 230 # define CONFIG_ENV_SIZE 0x2000 231 # define CONFIG_ENV_SECT_SIZE 0x20000 232 #endif 233 #undef CONFIG_ENV_OVERWRITE 234 235 /* FLASH organization */ 236 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 237 238 #define CONFIG_SYS_FLASH_CFI 239 #ifdef CONFIG_SYS_FLASH_CFI 240 241 # define CONFIG_FLASH_CFI_DRIVER 1 242 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 243 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 244 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 245 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 246 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 247 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 248 # define CONFIG_SYS_FLASH_CHECKSUM 249 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 250 251 #endif 252 253 /* 254 * This is setting for JFFS2 support in u-boot. 255 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 256 */ 257 #ifdef CONFIG_CMD_JFFS2 258 # define CONFIG_JFFS2_DEV "nor0" 259 # define CONFIG_JFFS2_PART_SIZE 0x01000000 260 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 261 #endif 262 263 /* Cache Configuration */ 264 #define CONFIG_SYS_CACHELINE_SIZE 16 265 266 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 267 CONFIG_SYS_INIT_RAM_SIZE - 8) 268 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 269 CONFIG_SYS_INIT_RAM_SIZE - 4) 270 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 271 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 272 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 273 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 274 CF_ACR_EN | CF_ACR_SM_ALL) 275 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 276 CF_CACR_ICINVA | CF_CACR_EUSP) 277 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 278 CF_CACR_DEC | CF_CACR_DDCM_P | \ 279 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 280 281 /*----------------------------------------------------------------------- 282 * Memory bank definitions 283 */ 284 /* 285 * CS0 - NOR Flash 16MB 286 * CS1 - Available 287 * CS2 - Available 288 * CS3 - Available 289 * CS4 - Available 290 * CS5 - Available 291 */ 292 293 /* Flash */ 294 #define CONFIG_SYS_CS0_BASE 0x00000000 295 #define CONFIG_SYS_CS0_MASK 0x00FF0001 296 #define CONFIG_SYS_CS0_CTRL 0x00004D80 297 298 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE 299 300 #endif /* _M54451EVB_H */ 301