1 /* 2 * Configuation settings for the Freescale MCF54451 EVB board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef _M54451EVB_H 31 #define _M54451EVB_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_MCF5445x /* define processor family */ 38 #define CONFIG_M54451 /* define processor type */ 39 #define CONFIG_M54451EVB /* M54451EVB board */ 40 41 #define CONFIG_MCFUART 42 #define CFG_UART_PORT (0) 43 #define CONFIG_BAUDRATE 115200 44 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 45 46 #undef CONFIG_WATCHDOG 47 48 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 49 50 /* 51 * BOOTP options 52 */ 53 #define CONFIG_BOOTP_BOOTFILESIZE 54 #define CONFIG_BOOTP_BOOTPATH 55 #define CONFIG_BOOTP_GATEWAY 56 #define CONFIG_BOOTP_HOSTNAME 57 58 /* Command line configuration */ 59 #include <config_cmd_default.h> 60 61 #define CONFIG_CMD_BOOTD 62 #define CONFIG_CMD_CACHE 63 #define CONFIG_CMD_DATE 64 #define CONFIG_CMD_DHCP 65 #define CONFIG_CMD_ELF 66 #define CONFIG_CMD_FLASH 67 #define CONFIG_CMD_I2C 68 #undef CONFIG_CMD_JFFS2 69 #define CONFIG_CMD_MEMORY 70 #define CONFIG_CMD_MISC 71 #define CONFIG_CMD_MII 72 #define CONFIG_CMD_NET 73 #define CONFIG_CMD_PING 74 #define CONFIG_CMD_REGINFO 75 #define CONFIG_CMD_SPI 76 #define CONFIG_CMD_SF 77 78 #undef CONFIG_CMD_LOADB 79 #undef CONFIG_CMD_LOADS 80 81 /* Network configuration */ 82 #define CONFIG_MCFFEC 83 #ifdef CONFIG_MCFFEC 84 # define CONFIG_NET_MULTI 1 85 # define CONFIG_MII 1 86 # define CONFIG_MII_INIT 1 87 # define CFG_DISCOVER_PHY 88 # define CFG_RX_ETH_BUFFER 8 89 # define CFG_FAULT_ECHO_LINK_DOWN 90 91 # define CFG_FEC0_PINMUX 0 92 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE 93 # define MCFFEC_TOUT_LOOP 50000 94 95 # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 96 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" 97 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 98 # define CONFIG_ETHPRIME "FEC0" 99 # define CONFIG_IPADDR 192.162.1.2 100 # define CONFIG_NETMASK 255.255.255.0 101 # define CONFIG_SERVERIP 192.162.1.1 102 # define CONFIG_GATEWAYIP 192.162.1.1 103 # define CONFIG_OVERWRITE_ETHADDR_ONCE 104 105 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ 106 # ifndef CFG_DISCOVER_PHY 107 # define FECDUPLEX FULL 108 # define FECSPEED _100BASET 109 # else 110 # ifndef CFG_FAULT_ECHO_LINK_DOWN 111 # define CFG_FAULT_ECHO_LINK_DOWN 112 # endif 113 # endif /* CFG_DISCOVER_PHY */ 114 #endif 115 116 #define CONFIG_HOSTNAME M54451EVB 117 #ifdef CFG_STMICRO_BOOT 118 /* ST Micro serial flash */ 119 #define CFG_LOAD_ADDR2 0x40010007 120 #define CONFIG_EXTRA_ENV_SETTINGS \ 121 "netdev=eth0\0" \ 122 "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ 123 "loadaddr=0x40010000\0" \ 124 "sbfhdr=sbfhdr.bin\0" \ 125 "uboot=u-boot.bin\0" \ 126 "load=tftp ${loadaddr} ${sbfhdr};" \ 127 "tftp " MK_STR(CFG_LOAD_ADDR2) " ${uboot} \0" \ 128 "upd=run load; run prog\0" \ 129 "prog=sf probe 0:1 10000 1;" \ 130 "sf erase 0 30000;" \ 131 "sf write ${loadaddr} 0 30000;" \ 132 "save\0" \ 133 "" 134 #else 135 #define CFG_UBOOT_END 0x3FFFF 136 #define CONFIG_EXTRA_ENV_SETTINGS \ 137 "netdev=eth0\0" \ 138 "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ 139 "loadaddr=40010000\0" \ 140 "u-boot=u-boot.bin\0" \ 141 "load=tftp ${loadaddr) ${u-boot}\0" \ 142 "upd=run load; run prog\0" \ 143 "prog=prot off 0 " MK_STR(CFG_UBOOT_END)\ 144 "; era 0 " MK_STR(CFG_UBOOT_END) \ 145 "2ffff;" \ 146 "cp.b ${loadaddr} 0 ${filesize};" \ 147 "save\0" \ 148 "" 149 #endif 150 151 /* Realtime clock */ 152 #define CONFIG_MCFRTC 153 #undef RTC_DEBUG 154 #define CFG_RTC_OSCILLATOR (32 * CFG_HZ) 155 156 /* Timer */ 157 #define CONFIG_MCFTMR 158 #undef CONFIG_MCFPIT 159 160 /* I2c */ 161 #define CONFIG_FSL_I2C 162 #define CONFIG_HARD_I2C /* I2C with hardware support */ 163 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 164 #define CFG_I2C_SPEED 80000 /* I2C speed and slave address */ 165 #define CFG_I2C_SLAVE 0x7F 166 #define CFG_I2C_OFFSET 0x58000 167 #define CFG_IMMR CFG_MBAR 168 169 /* DSPI and Serial Flash */ 170 #define CONFIG_CF_DSPI 171 #define CONFIG_SERIAL_FLASH 172 #define CONFIG_HARD_SPI 173 #define CFG_SER_FLASH_BASE 0x01000000 174 #define CFG_SBFHDR_SIZE 0x7 175 #ifdef CONFIG_CMD_SPI 176 # define CONFIG_SPI_FLASH 177 # define CONFIG_SPI_FLASH_STMICRO 178 179 # define CFG_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ 180 DSPI_DCTAR_CPOL | \ 181 DSPI_DCTAR_CPHA | \ 182 DSPI_DCTAR_PCSSCK_1CLK | \ 183 DSPI_DCTAR_PASC(0) | \ 184 DSPI_DCTAR_PDT(0) | \ 185 DSPI_DCTAR_CSSCK(0) | \ 186 DSPI_DCTAR_ASC(0) | \ 187 DSPI_DCTAR_PBR(0) | \ 188 DSPI_DCTAR_DT(1) | \ 189 DSPI_DCTAR_BR(1)) 190 #endif 191 192 /* Input, PCI, Flexbus, and VCO */ 193 #define CONFIG_EXTRA_CLOCK 194 195 #define CONFIG_PRAM 2048 /* 2048 KB */ 196 197 #define CFG_PROMPT "-> " 198 #define CFG_LONGHELP /* undef to save memory */ 199 200 #if defined(CONFIG_CMD_KGDB) 201 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 202 #else 203 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 204 #endif 205 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 206 #define CFG_MAXARGS 16 /* max number of command args */ 207 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 208 209 #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000) 210 211 #define CFG_HZ 1000 212 213 #define CFG_MBAR 0xFC000000 214 215 /* 216 * Low Level Configuration Settings 217 * (address mappings, register initial values, etc.) 218 * You should know what you are doing if you make changes here. 219 */ 220 221 /*----------------------------------------------------------------------- 222 * Definitions for initial stack pointer and data area (in DPRAM) 223 */ 224 #define CFG_INIT_RAM_ADDR 0x80000000 225 #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ 226 #define CFG_INIT_RAM_CTRL 0x221 227 #define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ 228 #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 32) 229 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 230 #define CFG_SBFHDR_DATA_OFFSET (CFG_INIT_RAM_END - 32) 231 232 /*----------------------------------------------------------------------- 233 * Start addresses for the final memory configuration 234 * (Set up by the startup code) 235 * Please note that CFG_SDRAM_BASE _must_ start at 0 236 */ 237 #define CFG_SDRAM_BASE 0x40000000 238 #define CFG_SDRAM_SIZE 128 /* SDRAM size in MB */ 239 #define CFG_SDRAM_CFG1 0x33633F30 240 #define CFG_SDRAM_CFG2 0x57670000 241 #define CFG_SDRAM_CTRL 0xE20D2C00 242 #define CFG_SDRAM_EMOD 0x80810000 243 #define CFG_SDRAM_MODE 0x008D0000 244 #define CFG_SDRAM_DRV_STRENGTH 0x44 245 246 #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 247 #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) 248 249 #ifdef CONFIG_CF_SBF 250 # define CFG_MONITOR_BASE (TEXT_BASE + 0x400) 251 #else 252 # define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) 253 #endif 254 #define CFG_BOOTPARAMS_LEN 64*1024 255 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 256 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 257 258 /* 259 * For booting Linux, the board info and command line data 260 * have to be in the first 8 MB of memory, since this is 261 * the maximum mapped by the Linux kernel during initialization ?? 262 */ 263 /* Initial Memory map for Linux */ 264 #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) 265 266 /* Configuration for environment 267 * Environment is embedded in u-boot in the second sector of the flash 268 */ 269 #if defined(CONFIG_CF_SBF) 270 # define CFG_ENV_IS_IN_SPI_FLASH 1 271 # define CFG_ENV_SPI_CS 1 272 # define CFG_ENV_OFFSET 0x20000 273 # define CFG_ENV_SIZE 0x2000 274 # define CFG_ENV_SECT_SIZE 0x10000 275 #else 276 # define CFG_ENV_IS_IN_FLASH 1 277 # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) 278 # define CFG_ENV_SECT_SIZE 0x2000 279 #endif 280 #undef CONFIG_ENV_OVERWRITE 281 #undef CFG_ENV_IS_EMBEDDED 282 283 /*----------------------------------------------------------------------- 284 * FLASH organization 285 */ 286 #ifdef CFG_STMICRO_BOOT 287 # define CFG_FLASH_BASE CFG_SER_FLASH_BASE 288 # define CFG_FLASH0_BASE CFG_SER_FLASH_BASE 289 # define CFG_FLASH1_BASE CFG_CS0_BASE 290 #endif 291 #ifdef CFG_SPANSION_BOOT 292 # define CFG_FLASH_BASE CFG_CS0_BASE 293 # define CFG_FLASH0_BASE CFG_CS0_BASE 294 # define CFG_FLASH1_BASE CFG_SER_FLASH_BASE 295 #endif 296 297 #define CFG_FLASH_CFI 298 #ifdef CFG_FLASH_CFI 299 300 # define CONFIG_FLASH_CFI_DRIVER 1 301 # define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 302 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT 303 # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ 304 # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 305 # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 306 # define CFG_FLASH_CHECKSUM 307 # define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE } 308 309 #endif 310 311 /* 312 * This is setting for JFFS2 support in u-boot. 313 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 314 */ 315 #ifdef CFG_SPANSION_BOOT 316 # define CONFIG_JFFS2_DEV "nor0" 317 # define CONFIG_JFFS2_PART_SIZE 0x01000000 318 # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) 319 #endif 320 #ifdef CFG_STMICRO_BOOT 321 # define CONFIG_JFFS2_DEV "nor0" 322 # define CONFIG_JFFS2_PART_SIZE 0x01000000 323 # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) 324 #endif 325 326 /*----------------------------------------------------------------------- 327 * Cache Configuration 328 */ 329 #define CFG_CACHELINE_SIZE 16 330 331 /*----------------------------------------------------------------------- 332 * Memory bank definitions 333 */ 334 /* 335 * CS0 - NOR Flash 8MB 336 * CS1 - Available 337 * CS2 - Available 338 * CS3 - Available 339 * CS4 - Available 340 * CS5 - Available 341 */ 342 343 /* SPANSION Flash */ 344 #define CFG_CS0_BASE 0x00000000 345 #define CFG_CS0_MASK 0x007F0001 346 #define CFG_CS0_CTRL 0x00001180 347 348 #define CFG_SPANSION_BASE CFG_CS0_BASE 349 350 #endif /* _M54451EVB_H */ 351