1 /* 2 * Configuation settings for the Freescale MCF54451 EVB board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54451EVB_H 15 #define _M54451EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54451EVB /* M54451EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 26 #undef CONFIG_WATCHDOG 27 28 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 29 30 /* 31 * BOOTP options 32 */ 33 #define CONFIG_BOOTP_BOOTFILESIZE 34 #define CONFIG_BOOTP_BOOTPATH 35 #define CONFIG_BOOTP_GATEWAY 36 #define CONFIG_BOOTP_HOSTNAME 37 38 /* Network configuration */ 39 #define CONFIG_MCFFEC 40 #ifdef CONFIG_MCFFEC 41 # define CONFIG_MII 1 42 # define CONFIG_MII_INIT 1 43 # define CONFIG_SYS_DISCOVER_PHY 44 # define CONFIG_SYS_RX_ETH_BUFFER 8 45 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 46 47 # define CONFIG_SYS_FEC0_PINMUX 0 48 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 49 # define MCFFEC_TOUT_LOOP 50000 50 51 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)" 52 # define CONFIG_ETHPRIME "FEC0" 53 # define CONFIG_IPADDR 192.162.1.2 54 # define CONFIG_NETMASK 255.255.255.0 55 # define CONFIG_SERVERIP 192.162.1.1 56 # define CONFIG_GATEWAYIP 192.162.1.1 57 58 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 59 # ifndef CONFIG_SYS_DISCOVER_PHY 60 # define FECDUPLEX FULL 61 # define FECSPEED _100BASET 62 # else 63 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 64 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 65 # endif 66 # endif /* CONFIG_SYS_DISCOVER_PHY */ 67 #endif 68 69 #define CONFIG_HOSTNAME M54451EVB 70 #ifdef CONFIG_SYS_STMICRO_BOOT 71 /* ST Micro serial flash */ 72 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 73 #define CONFIG_EXTRA_ENV_SETTINGS \ 74 "netdev=eth0\0" \ 75 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 76 "loadaddr=0x40010000\0" \ 77 "sbfhdr=sbfhdr.bin\0" \ 78 "uboot=u-boot.bin\0" \ 79 "load=tftp ${loadaddr} ${sbfhdr};" \ 80 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 81 "upd=run load; run prog\0" \ 82 "prog=sf probe 0:1 1000000 3;" \ 83 "sf erase 0 30000;" \ 84 "sf write ${loadaddr} 0 30000;" \ 85 "save\0" \ 86 "" 87 #else 88 #define CONFIG_SYS_UBOOT_END 0x3FFFF 89 #define CONFIG_EXTRA_ENV_SETTINGS \ 90 "netdev=eth0\0" \ 91 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 92 "loadaddr=40010000\0" \ 93 "u-boot=u-boot.bin\0" \ 94 "load=tftp ${loadaddr) ${u-boot}\0" \ 95 "upd=run load; run prog\0" \ 96 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ 97 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ 98 "cp.b ${loadaddr} 0 ${filesize};" \ 99 "save\0" \ 100 "" 101 #endif 102 103 /* Realtime clock */ 104 #define CONFIG_MCFRTC 105 #undef RTC_DEBUG 106 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 107 108 /* Timer */ 109 #define CONFIG_MCFTMR 110 #undef CONFIG_MCFPIT 111 112 /* I2c */ 113 #define CONFIG_SYS_I2C 114 #define CONFIG_SYS_I2C_FSL 115 #define CONFIG_SYS_FSL_I2C_SPEED 80000 116 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 117 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 118 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 119 120 /* DSPI and Serial Flash */ 121 #define CONFIG_CF_SPI 122 #define CONFIG_CF_DSPI 123 #define CONFIG_SERIAL_FLASH 124 #define CONFIG_HARD_SPI 125 #define CONFIG_SYS_SBFHDR_SIZE 0x7 126 #ifdef CONFIG_CMD_SPI 127 128 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 129 DSPI_CTAR_PCSSCK_1CLK | \ 130 DSPI_CTAR_PASC(0) | \ 131 DSPI_CTAR_PDT(0) | \ 132 DSPI_CTAR_CSSCK(0) | \ 133 DSPI_CTAR_ASC(0) | \ 134 DSPI_CTAR_DT(1)) 135 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 136 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 137 #endif 138 139 /* Input, PCI, Flexbus, and VCO */ 140 #define CONFIG_EXTRA_CLOCK 141 142 #define CONFIG_PRAM 2048 /* 2048 KB */ 143 144 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 145 146 #if defined(CONFIG_CMD_KGDB) 147 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 148 #else 149 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 150 #endif 151 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 152 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 153 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 154 155 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 156 157 #define CONFIG_SYS_MBAR 0xFC000000 158 159 /* 160 * Low Level Configuration Settings 161 * (address mappings, register initial values, etc.) 162 * You should know what you are doing if you make changes here. 163 */ 164 165 /*----------------------------------------------------------------------- 166 * Definitions for initial stack pointer and data area (in DPRAM) 167 */ 168 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 169 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 170 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 171 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 172 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 173 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 174 175 /*----------------------------------------------------------------------- 176 * Start addresses for the final memory configuration 177 * (Set up by the startup code) 178 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 179 */ 180 #define CONFIG_SYS_SDRAM_BASE 0x40000000 181 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 182 #define CONFIG_SYS_SDRAM_CFG1 0x33633F30 183 #define CONFIG_SYS_SDRAM_CFG2 0x57670000 184 #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 185 #define CONFIG_SYS_SDRAM_EMOD 0x80810000 186 #define CONFIG_SYS_SDRAM_MODE 0x008D0000 187 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 188 189 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 190 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 191 192 #ifdef CONFIG_CF_SBF 193 # define CONFIG_SERIAL_BOOT 194 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 195 #else 196 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 197 #endif 198 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 199 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 200 201 /* Reserve 256 kB for malloc() */ 202 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 203 /* 204 * For booting Linux, the board info and command line data 205 * have to be in the first 8 MB of memory, since this is 206 * the maximum mapped by the Linux kernel during initialization ?? 207 */ 208 /* Initial Memory map for Linux */ 209 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 210 211 /* Configuration for environment 212 * Environment is not embedded in u-boot. First time runing may have env 213 * crc error warning if there is no correct environment on the flash. 214 */ 215 #if defined(CONFIG_SYS_STMICRO_BOOT) 216 # define CONFIG_ENV_SPI_CS 1 217 # define CONFIG_ENV_OFFSET 0x20000 218 # define CONFIG_ENV_SIZE 0x2000 219 # define CONFIG_ENV_SECT_SIZE 0x10000 220 #else 221 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 222 # define CONFIG_ENV_SIZE 0x2000 223 # define CONFIG_ENV_SECT_SIZE 0x20000 224 #endif 225 #undef CONFIG_ENV_OVERWRITE 226 227 /* FLASH organization */ 228 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 229 230 #define CONFIG_SYS_FLASH_CFI 231 #ifdef CONFIG_SYS_FLASH_CFI 232 233 # define CONFIG_FLASH_CFI_DRIVER 1 234 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 235 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 236 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 237 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 238 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 239 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 240 # define CONFIG_SYS_FLASH_CHECKSUM 241 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 242 243 #endif 244 245 /* 246 * This is setting for JFFS2 support in u-boot. 247 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 248 */ 249 #ifdef CONFIG_CMD_JFFS2 250 # define CONFIG_JFFS2_DEV "nor0" 251 # define CONFIG_JFFS2_PART_SIZE 0x01000000 252 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 253 #endif 254 255 /* Cache Configuration */ 256 #define CONFIG_SYS_CACHELINE_SIZE 16 257 258 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 259 CONFIG_SYS_INIT_RAM_SIZE - 8) 260 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 261 CONFIG_SYS_INIT_RAM_SIZE - 4) 262 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 263 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 264 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 265 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 266 CF_ACR_EN | CF_ACR_SM_ALL) 267 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 268 CF_CACR_ICINVA | CF_CACR_EUSP) 269 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 270 CF_CACR_DEC | CF_CACR_DDCM_P | \ 271 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 272 273 /*----------------------------------------------------------------------- 274 * Memory bank definitions 275 */ 276 /* 277 * CS0 - NOR Flash 16MB 278 * CS1 - Available 279 * CS2 - Available 280 * CS3 - Available 281 * CS4 - Available 282 * CS5 - Available 283 */ 284 285 /* Flash */ 286 #define CONFIG_SYS_CS0_BASE 0x00000000 287 #define CONFIG_SYS_CS0_MASK 0x00FF0001 288 #define CONFIG_SYS_CS0_CTRL 0x00004D80 289 290 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE 291 292 #endif /* _M54451EVB_H */ 293