1 /* 2 * Configuation settings for the Freescale MCF54451 EVB board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54451EVB_H 15 #define _M54451EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54451EVB /* M54451EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 26 #undef CONFIG_WATCHDOG 27 28 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 29 30 /* 31 * BOOTP options 32 */ 33 #define CONFIG_BOOTP_BOOTFILESIZE 34 #define CONFIG_BOOTP_BOOTPATH 35 #define CONFIG_BOOTP_GATEWAY 36 #define CONFIG_BOOTP_HOSTNAME 37 38 /* Network configuration */ 39 #define CONFIG_MCFFEC 40 #ifdef CONFIG_MCFFEC 41 # define CONFIG_MII 1 42 # define CONFIG_MII_INIT 1 43 # define CONFIG_SYS_DISCOVER_PHY 44 # define CONFIG_SYS_RX_ETH_BUFFER 8 45 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 46 47 # define CONFIG_SYS_FEC0_PINMUX 0 48 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 49 # define MCFFEC_TOUT_LOOP 50000 50 51 # define CONFIG_ETHPRIME "FEC0" 52 # define CONFIG_IPADDR 192.162.1.2 53 # define CONFIG_NETMASK 255.255.255.0 54 # define CONFIG_SERVERIP 192.162.1.1 55 # define CONFIG_GATEWAYIP 192.162.1.1 56 57 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 58 # ifndef CONFIG_SYS_DISCOVER_PHY 59 # define FECDUPLEX FULL 60 # define FECSPEED _100BASET 61 # else 62 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 63 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 64 # endif 65 # endif /* CONFIG_SYS_DISCOVER_PHY */ 66 #endif 67 68 #define CONFIG_HOSTNAME M54451EVB 69 #ifdef CONFIG_SYS_STMICRO_BOOT 70 /* ST Micro serial flash */ 71 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 72 #define CONFIG_EXTRA_ENV_SETTINGS \ 73 "netdev=eth0\0" \ 74 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 75 "loadaddr=0x40010000\0" \ 76 "sbfhdr=sbfhdr.bin\0" \ 77 "uboot=u-boot.bin\0" \ 78 "load=tftp ${loadaddr} ${sbfhdr};" \ 79 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 80 "upd=run load; run prog\0" \ 81 "prog=sf probe 0:1 1000000 3;" \ 82 "sf erase 0 30000;" \ 83 "sf write ${loadaddr} 0 30000;" \ 84 "save\0" \ 85 "" 86 #else 87 #define CONFIG_SYS_UBOOT_END 0x3FFFF 88 #define CONFIG_EXTRA_ENV_SETTINGS \ 89 "netdev=eth0\0" \ 90 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 91 "loadaddr=40010000\0" \ 92 "u-boot=u-boot.bin\0" \ 93 "load=tftp ${loadaddr) ${u-boot}\0" \ 94 "upd=run load; run prog\0" \ 95 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ 96 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ 97 "cp.b ${loadaddr} 0 ${filesize};" \ 98 "save\0" \ 99 "" 100 #endif 101 102 /* Realtime clock */ 103 #define CONFIG_MCFRTC 104 #undef RTC_DEBUG 105 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 106 107 /* Timer */ 108 #define CONFIG_MCFTMR 109 #undef CONFIG_MCFPIT 110 111 /* I2c */ 112 #define CONFIG_SYS_I2C 113 #define CONFIG_SYS_I2C_FSL 114 #define CONFIG_SYS_FSL_I2C_SPEED 80000 115 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 116 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 117 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 118 119 /* DSPI and Serial Flash */ 120 #define CONFIG_CF_SPI 121 #define CONFIG_CF_DSPI 122 #define CONFIG_SERIAL_FLASH 123 #define CONFIG_HARD_SPI 124 #define CONFIG_SYS_SBFHDR_SIZE 0x7 125 #ifdef CONFIG_CMD_SPI 126 127 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 128 DSPI_CTAR_PCSSCK_1CLK | \ 129 DSPI_CTAR_PASC(0) | \ 130 DSPI_CTAR_PDT(0) | \ 131 DSPI_CTAR_CSSCK(0) | \ 132 DSPI_CTAR_ASC(0) | \ 133 DSPI_CTAR_DT(1)) 134 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 135 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 136 #endif 137 138 /* Input, PCI, Flexbus, and VCO */ 139 #define CONFIG_EXTRA_CLOCK 140 141 #define CONFIG_PRAM 2048 /* 2048 KB */ 142 143 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 144 145 #if defined(CONFIG_CMD_KGDB) 146 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 147 #else 148 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 149 #endif 150 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 151 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 152 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 153 154 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 155 156 #define CONFIG_SYS_MBAR 0xFC000000 157 158 /* 159 * Low Level Configuration Settings 160 * (address mappings, register initial values, etc.) 161 * You should know what you are doing if you make changes here. 162 */ 163 164 /*----------------------------------------------------------------------- 165 * Definitions for initial stack pointer and data area (in DPRAM) 166 */ 167 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 168 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 169 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 170 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 171 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 172 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 173 174 /*----------------------------------------------------------------------- 175 * Start addresses for the final memory configuration 176 * (Set up by the startup code) 177 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 178 */ 179 #define CONFIG_SYS_SDRAM_BASE 0x40000000 180 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 181 #define CONFIG_SYS_SDRAM_CFG1 0x33633F30 182 #define CONFIG_SYS_SDRAM_CFG2 0x57670000 183 #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 184 #define CONFIG_SYS_SDRAM_EMOD 0x80810000 185 #define CONFIG_SYS_SDRAM_MODE 0x008D0000 186 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 187 188 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 189 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 190 191 #ifdef CONFIG_CF_SBF 192 # define CONFIG_SERIAL_BOOT 193 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 194 #else 195 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 196 #endif 197 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 198 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 199 200 /* Reserve 256 kB for malloc() */ 201 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 202 /* 203 * For booting Linux, the board info and command line data 204 * have to be in the first 8 MB of memory, since this is 205 * the maximum mapped by the Linux kernel during initialization ?? 206 */ 207 /* Initial Memory map for Linux */ 208 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 209 210 /* Configuration for environment 211 * Environment is not embedded in u-boot. First time runing may have env 212 * crc error warning if there is no correct environment on the flash. 213 */ 214 #if defined(CONFIG_SYS_STMICRO_BOOT) 215 # define CONFIG_ENV_SPI_CS 1 216 # define CONFIG_ENV_OFFSET 0x20000 217 # define CONFIG_ENV_SIZE 0x2000 218 # define CONFIG_ENV_SECT_SIZE 0x10000 219 #else 220 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 221 # define CONFIG_ENV_SIZE 0x2000 222 # define CONFIG_ENV_SECT_SIZE 0x20000 223 #endif 224 #undef CONFIG_ENV_OVERWRITE 225 226 /* FLASH organization */ 227 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 228 229 #define CONFIG_SYS_FLASH_CFI 230 #ifdef CONFIG_SYS_FLASH_CFI 231 232 # define CONFIG_FLASH_CFI_DRIVER 1 233 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 234 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 235 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 236 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 237 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 238 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 239 # define CONFIG_SYS_FLASH_CHECKSUM 240 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 241 242 #endif 243 244 /* 245 * This is setting for JFFS2 support in u-boot. 246 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 247 */ 248 #ifdef CONFIG_CMD_JFFS2 249 # define CONFIG_JFFS2_DEV "nor0" 250 # define CONFIG_JFFS2_PART_SIZE 0x01000000 251 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 252 #endif 253 254 /* Cache Configuration */ 255 #define CONFIG_SYS_CACHELINE_SIZE 16 256 257 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 258 CONFIG_SYS_INIT_RAM_SIZE - 8) 259 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 260 CONFIG_SYS_INIT_RAM_SIZE - 4) 261 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 262 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 263 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 264 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 265 CF_ACR_EN | CF_ACR_SM_ALL) 266 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 267 CF_CACR_ICINVA | CF_CACR_EUSP) 268 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 269 CF_CACR_DEC | CF_CACR_DDCM_P | \ 270 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 271 272 /*----------------------------------------------------------------------- 273 * Memory bank definitions 274 */ 275 /* 276 * CS0 - NOR Flash 16MB 277 * CS1 - Available 278 * CS2 - Available 279 * CS3 - Available 280 * CS4 - Available 281 * CS5 - Available 282 */ 283 284 /* Flash */ 285 #define CONFIG_SYS_CS0_BASE 0x00000000 286 #define CONFIG_SYS_CS0_MASK 0x00FF0001 287 #define CONFIG_SYS_CS0_CTRL 0x00004D80 288 289 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE 290 291 #endif /* _M54451EVB_H */ 292