1 /* 2 * Configuation settings for the Freescale MCF54451 EVB board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54451EVB_H 15 #define _M54451EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54451EVB /* M54451EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 26 #undef CONFIG_WATCHDOG 27 28 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 29 30 /* 31 * BOOTP options 32 */ 33 #define CONFIG_BOOTP_BOOTFILESIZE 34 #define CONFIG_BOOTP_BOOTPATH 35 #define CONFIG_BOOTP_GATEWAY 36 #define CONFIG_BOOTP_HOSTNAME 37 38 /* Command line configuration */ 39 #define CONFIG_CMD_DATE 40 #undef CONFIG_CMD_JFFS2 41 #define CONFIG_CMD_REGINFO 42 43 /* Network configuration */ 44 #define CONFIG_MCFFEC 45 #ifdef CONFIG_MCFFEC 46 # define CONFIG_MII 1 47 # define CONFIG_MII_INIT 1 48 # define CONFIG_SYS_DISCOVER_PHY 49 # define CONFIG_SYS_RX_ETH_BUFFER 8 50 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 51 52 # define CONFIG_SYS_FEC0_PINMUX 0 53 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 54 # define MCFFEC_TOUT_LOOP 50000 55 56 # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)" 57 # define CONFIG_ETHPRIME "FEC0" 58 # define CONFIG_IPADDR 192.162.1.2 59 # define CONFIG_NETMASK 255.255.255.0 60 # define CONFIG_SERVERIP 192.162.1.1 61 # define CONFIG_GATEWAYIP 192.162.1.1 62 63 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 64 # ifndef CONFIG_SYS_DISCOVER_PHY 65 # define FECDUPLEX FULL 66 # define FECSPEED _100BASET 67 # else 68 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 69 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 70 # endif 71 # endif /* CONFIG_SYS_DISCOVER_PHY */ 72 #endif 73 74 #define CONFIG_HOSTNAME M54451EVB 75 #ifdef CONFIG_SYS_STMICRO_BOOT 76 /* ST Micro serial flash */ 77 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 78 #define CONFIG_EXTRA_ENV_SETTINGS \ 79 "netdev=eth0\0" \ 80 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 81 "loadaddr=0x40010000\0" \ 82 "sbfhdr=sbfhdr.bin\0" \ 83 "uboot=u-boot.bin\0" \ 84 "load=tftp ${loadaddr} ${sbfhdr};" \ 85 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 86 "upd=run load; run prog\0" \ 87 "prog=sf probe 0:1 1000000 3;" \ 88 "sf erase 0 30000;" \ 89 "sf write ${loadaddr} 0 30000;" \ 90 "save\0" \ 91 "" 92 #else 93 #define CONFIG_SYS_UBOOT_END 0x3FFFF 94 #define CONFIG_EXTRA_ENV_SETTINGS \ 95 "netdev=eth0\0" \ 96 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 97 "loadaddr=40010000\0" \ 98 "u-boot=u-boot.bin\0" \ 99 "load=tftp ${loadaddr) ${u-boot}\0" \ 100 "upd=run load; run prog\0" \ 101 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ 102 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ 103 "cp.b ${loadaddr} 0 ${filesize};" \ 104 "save\0" \ 105 "" 106 #endif 107 108 /* Realtime clock */ 109 #define CONFIG_MCFRTC 110 #undef RTC_DEBUG 111 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 112 113 /* Timer */ 114 #define CONFIG_MCFTMR 115 #undef CONFIG_MCFPIT 116 117 /* I2c */ 118 #define CONFIG_SYS_I2C 119 #define CONFIG_SYS_I2C_FSL 120 #define CONFIG_SYS_FSL_I2C_SPEED 80000 121 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 122 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 123 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 124 125 /* DSPI and Serial Flash */ 126 #define CONFIG_CF_SPI 127 #define CONFIG_CF_DSPI 128 #define CONFIG_SERIAL_FLASH 129 #define CONFIG_HARD_SPI 130 #define CONFIG_SYS_SBFHDR_SIZE 0x7 131 #ifdef CONFIG_CMD_SPI 132 133 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 134 DSPI_CTAR_PCSSCK_1CLK | \ 135 DSPI_CTAR_PASC(0) | \ 136 DSPI_CTAR_PDT(0) | \ 137 DSPI_CTAR_CSSCK(0) | \ 138 DSPI_CTAR_ASC(0) | \ 139 DSPI_CTAR_DT(1)) 140 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 141 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 142 #endif 143 144 /* Input, PCI, Flexbus, and VCO */ 145 #define CONFIG_EXTRA_CLOCK 146 147 #define CONFIG_PRAM 2048 /* 2048 KB */ 148 149 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 150 151 #if defined(CONFIG_CMD_KGDB) 152 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 153 #else 154 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 155 #endif 156 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 157 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 158 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 159 160 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 161 162 #define CONFIG_SYS_MBAR 0xFC000000 163 164 /* 165 * Low Level Configuration Settings 166 * (address mappings, register initial values, etc.) 167 * You should know what you are doing if you make changes here. 168 */ 169 170 /*----------------------------------------------------------------------- 171 * Definitions for initial stack pointer and data area (in DPRAM) 172 */ 173 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 174 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 175 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 176 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 177 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 178 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 179 180 /*----------------------------------------------------------------------- 181 * Start addresses for the final memory configuration 182 * (Set up by the startup code) 183 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 184 */ 185 #define CONFIG_SYS_SDRAM_BASE 0x40000000 186 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 187 #define CONFIG_SYS_SDRAM_CFG1 0x33633F30 188 #define CONFIG_SYS_SDRAM_CFG2 0x57670000 189 #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 190 #define CONFIG_SYS_SDRAM_EMOD 0x80810000 191 #define CONFIG_SYS_SDRAM_MODE 0x008D0000 192 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 193 194 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 195 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 196 197 #ifdef CONFIG_CF_SBF 198 # define CONFIG_SERIAL_BOOT 199 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 200 #else 201 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 202 #endif 203 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 204 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 205 206 /* Reserve 256 kB for malloc() */ 207 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 208 /* 209 * For booting Linux, the board info and command line data 210 * have to be in the first 8 MB of memory, since this is 211 * the maximum mapped by the Linux kernel during initialization ?? 212 */ 213 /* Initial Memory map for Linux */ 214 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 215 216 /* Configuration for environment 217 * Environment is not embedded in u-boot. First time runing may have env 218 * crc error warning if there is no correct environment on the flash. 219 */ 220 #if defined(CONFIG_SYS_STMICRO_BOOT) 221 # define CONFIG_ENV_IS_IN_SPI_FLASH 1 222 # define CONFIG_ENV_SPI_CS 1 223 # define CONFIG_ENV_OFFSET 0x20000 224 # define CONFIG_ENV_SIZE 0x2000 225 # define CONFIG_ENV_SECT_SIZE 0x10000 226 #else 227 # define CONFIG_ENV_IS_IN_FLASH 1 228 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 229 # define CONFIG_ENV_SIZE 0x2000 230 # define CONFIG_ENV_SECT_SIZE 0x20000 231 #endif 232 #undef CONFIG_ENV_OVERWRITE 233 234 /* FLASH organization */ 235 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 236 237 #define CONFIG_SYS_FLASH_CFI 238 #ifdef CONFIG_SYS_FLASH_CFI 239 240 # define CONFIG_FLASH_CFI_DRIVER 1 241 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 242 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 243 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 244 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 245 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 246 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 247 # define CONFIG_SYS_FLASH_CHECKSUM 248 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 249 250 #endif 251 252 /* 253 * This is setting for JFFS2 support in u-boot. 254 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 255 */ 256 #ifdef CONFIG_CMD_JFFS2 257 # define CONFIG_JFFS2_DEV "nor0" 258 # define CONFIG_JFFS2_PART_SIZE 0x01000000 259 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 260 #endif 261 262 /* Cache Configuration */ 263 #define CONFIG_SYS_CACHELINE_SIZE 16 264 265 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 266 CONFIG_SYS_INIT_RAM_SIZE - 8) 267 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 268 CONFIG_SYS_INIT_RAM_SIZE - 4) 269 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 270 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 271 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 272 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 273 CF_ACR_EN | CF_ACR_SM_ALL) 274 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 275 CF_CACR_ICINVA | CF_CACR_EUSP) 276 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 277 CF_CACR_DEC | CF_CACR_DDCM_P | \ 278 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 279 280 /*----------------------------------------------------------------------- 281 * Memory bank definitions 282 */ 283 /* 284 * CS0 - NOR Flash 16MB 285 * CS1 - Available 286 * CS2 - Available 287 * CS3 - Available 288 * CS4 - Available 289 * CS5 - Available 290 */ 291 292 /* Flash */ 293 #define CONFIG_SYS_CS0_BASE 0x00000000 294 #define CONFIG_SYS_CS0_MASK 0x00FF0001 295 #define CONFIG_SYS_CS0_CTRL 0x00004D80 296 297 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE 298 299 #endif /* _M54451EVB_H */ 300