1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Freescale MCF54418 TWR board. 4 * 5 * Copyright 2010-2012 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M54418TWR_H 14 #define _M54418TWR_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21 #define CONFIG_MCFUART 22 #define CONFIG_SYS_UART_PORT (0) 23 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 24 25 #define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*) 26 27 #undef CONFIG_WATCHDOG 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 36 /* 37 * NAND FLASH 38 */ 39 #ifdef CONFIG_CMD_NAND 40 #define CONFIG_JFFS2_NAND 41 #define CONFIG_NAND_FSL_NFC 42 #define CONFIG_SYS_NAND_BASE 0xFC0FC000 43 #define CONFIG_SYS_MAX_NAND_DEVICE 1 44 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE 45 #define CONFIG_SYS_NAND_SELECT_DEVICE 46 #endif 47 48 /* Network configuration */ 49 #define CONFIG_MCFFEC 50 #ifdef CONFIG_MCFFEC 51 #define CONFIG_MII_INIT 1 52 #define CONFIG_SYS_DISCOVER_PHY 53 #define CONFIG_SYS_RX_ETH_BUFFER 2 54 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 55 #define CONFIG_SYS_TX_ETH_BUFFER 2 56 #define CONFIG_HAS_ETH1 57 58 #define CONFIG_SYS_FEC0_PINMUX 0 59 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 60 #define CONFIG_SYS_FEC1_PINMUX 0 61 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE 62 #define MCFFEC_TOUT_LOOP 50000 63 #define CONFIG_SYS_FEC0_PHYADDR 0 64 #define CONFIG_SYS_FEC1_PHYADDR 1 65 66 #define CONFIG_ETHPRIME "FEC0" 67 #define CONFIG_IPADDR 192.168.1.2 68 #define CONFIG_NETMASK 255.255.255.0 69 #define CONFIG_SERVERIP 192.168.1.1 70 #define CONFIG_GATEWAYIP 192.168.1.1 71 72 #define CONFIG_SYS_FEC_BUF_USE_SRAM 73 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 74 #ifndef CONFIG_SYS_DISCOVER_PHY 75 #define FECDUPLEX FULL 76 #define FECSPEED _100BASET 77 #define LINKSTATUS 1 78 #else 79 #define LINKSTATUS 0 80 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 81 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 82 #endif 83 #endif /* CONFIG_SYS_DISCOVER_PHY */ 84 #endif 85 86 #define CONFIG_HOSTNAME "M54418TWR" 87 88 #if defined(CONFIG_CF_SBF) 89 /* ST Micro serial flash */ 90 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 91 #define CONFIG_EXTRA_ENV_SETTINGS \ 92 "netdev=eth0\0" \ 93 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 94 "loadaddr=0x40010000\0" \ 95 "sbfhdr=sbfhdr.bin\0" \ 96 "uboot=u-boot.bin\0" \ 97 "load=tftp ${loadaddr} ${sbfhdr};" \ 98 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 99 "upd=run load; run prog\0" \ 100 "prog=sf probe 0:1 1000000 3;" \ 101 "sf erase 0 40000;" \ 102 "sf write ${loadaddr} 0 40000;" \ 103 "save\0" \ 104 "" 105 #elif defined(CONFIG_SYS_NAND_BOOT) 106 #define CONFIG_EXTRA_ENV_SETTINGS \ 107 "netdev=eth0\0" \ 108 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 109 "loadaddr=0x40010000\0" \ 110 "u-boot=u-boot.bin\0" \ 111 "load=tftp ${loadaddr} ${u-boot};\0" \ 112 "upd=run load; run prog\0" \ 113 "prog=nand device 0;" \ 114 "nand erase 0 40000;" \ 115 "nb_update ${loadaddr} ${filesize};" \ 116 "save\0" \ 117 "" 118 #else 119 #define CONFIG_SYS_UBOOT_END 0x3FFFF 120 #define CONFIG_EXTRA_ENV_SETTINGS \ 121 "netdev=eth0\0" \ 122 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 123 "loadaddr=40010000\0" \ 124 "u-boot=u-boot.bin\0" \ 125 "load=tftp ${loadaddr) ${u-boot}\0" \ 126 "upd=run load; run prog\0" \ 127 "prog=prot off mram" " ;" \ 128 "cp.b ${loadaddr} 0 ${filesize};" \ 129 "save\0" \ 130 "" 131 #endif 132 133 /* Realtime clock */ 134 #undef CONFIG_MCFRTC 135 #define CONFIG_RTC_MCFRRTC 136 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 137 138 /* Timer */ 139 #define CONFIG_MCFTMR 140 #undef CONFIG_MCFPIT 141 142 /* I2c */ 143 #undef CONFIG_SYS_FSL_I2C 144 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 145 /* I2C speed and slave address */ 146 #define CONFIG_SYS_I2C_SPEED 80000 147 #define CONFIG_SYS_I2C_SLAVE 0x7F 148 #define CONFIG_SYS_I2C_OFFSET 0x58000 149 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 150 151 /* DSPI and Serial Flash */ 152 #define CONFIG_CF_DSPI 153 #define CONFIG_SERIAL_FLASH 154 #define CONFIG_HARD_SPI 155 #define CONFIG_SYS_SBFHDR_SIZE 0x7 156 #ifdef CONFIG_CMD_SPI 157 158 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 159 DSPI_CTAR_PCSSCK_1CLK | \ 160 DSPI_CTAR_PASC(0) | \ 161 DSPI_CTAR_PDT(0) | \ 162 DSPI_CTAR_CSSCK(0) | \ 163 DSPI_CTAR_ASC(0) | \ 164 DSPI_CTAR_DT(1)) 165 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 166 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 167 #endif 168 169 /* Input, PCI, Flexbus, and VCO */ 170 #define CONFIG_EXTRA_CLOCK 171 172 #define CONFIG_PRAM 2048 /* 2048 KB */ 173 174 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 175 176 #define CONFIG_SYS_MBAR 0xFC000000 177 178 /* 179 * Low Level Configuration Settings 180 * (address mappings, register initial values, etc.) 181 * You should know what you are doing if you make changes here. 182 */ 183 184 /*----------------------------------------------------------------------- 185 * Definitions for initial stack pointer and data area (in DPRAM) 186 */ 187 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 188 /* End of used area in internal SRAM */ 189 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 190 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 191 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ 192 GENERATED_GBL_DATA_SIZE) - 32) 193 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 194 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 195 196 /*----------------------------------------------------------------------- 197 * Start addresses for the final memory configuration 198 * (Set up by the startup code) 199 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 200 */ 201 #define CONFIG_SYS_SDRAM_BASE 0x40000000 202 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 203 204 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) 205 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 206 #define CONFIG_SYS_DRAM_TEST 207 208 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) 209 #define CONFIG_SERIAL_BOOT 210 #endif 211 212 #if defined(CONFIG_SERIAL_BOOT) 213 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 214 #else 215 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 216 #endif 217 218 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 219 /* Reserve 256 kB for Monitor */ 220 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 221 /* Reserve 256 kB for malloc() */ 222 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 223 224 /* 225 * For booting Linux, the board info and command line data 226 * have to be in the first 8 MB of memory, since this is 227 * the maximum mapped by the Linux kernel during initialization ?? 228 */ 229 /* Initial Memory map for Linux */ 230 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 231 (CONFIG_SYS_SDRAM_SIZE << 20)) 232 233 /* Configuration for environment 234 * Environment is embedded in u-boot in the second sector of the flash 235 */ 236 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ 237 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ 238 #define CONFIG_ENV_SIZE 0x1000 239 #endif 240 241 #if defined(CONFIG_CF_SBF) 242 #define CONFIG_ENV_SPI_CS 1 243 #define CONFIG_ENV_OFFSET 0x40000 244 #define CONFIG_ENV_SIZE 0x2000 245 #define CONFIG_ENV_SECT_SIZE 0x10000 246 #endif 247 #if defined(CONFIG_SYS_NAND_BOOT) 248 #define CONFIG_ENV_OFFSET 0x80000 249 #define CONFIG_ENV_SIZE 0x20000 250 #define CONFIG_ENV_SECT_SIZE 0x20000 251 #endif 252 #undef CONFIG_ENV_OVERWRITE 253 254 /* FLASH organization */ 255 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 256 257 #undef CONFIG_SYS_FLASH_CFI 258 #ifdef CONFIG_SYS_FLASH_CFI 259 260 #define CONFIG_FLASH_CFI_DRIVER 1 261 /* Max size that the board might have */ 262 #define CONFIG_SYS_FLASH_SIZE 0x1000000 263 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 264 /* max number of memory banks */ 265 #define CONFIG_SYS_MAX_FLASH_BANKS 1 266 /* max number of sectors on one chip */ 267 #define CONFIG_SYS_MAX_FLASH_SECT 270 268 /* "Real" (hardware) sectors protection */ 269 #define CONFIG_SYS_FLASH_PROTECTION 270 #define CONFIG_SYS_FLASH_CHECKSUM 271 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 272 #else 273 /* max number of sectors on one chip */ 274 #define CONFIG_SYS_MAX_FLASH_SECT 270 275 /* max number of sectors on one chip */ 276 #define CONFIG_SYS_MAX_FLASH_BANKS 0 277 #endif 278 279 /* 280 * This is setting for JFFS2 support in u-boot. 281 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 282 */ 283 #ifdef CONFIG_CMD_JFFS2 284 #define CONFIG_JFFS2_DEV "nand0" 285 #define CONFIG_JFFS2_PART_OFFSET (0x800000) 286 287 #endif 288 289 /* Cache Configuration */ 290 #define CONFIG_SYS_CACHELINE_SIZE 16 291 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 292 CONFIG_SYS_INIT_RAM_SIZE - 8) 293 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 294 CONFIG_SYS_INIT_RAM_SIZE - 4) 295 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 296 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 297 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 298 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 299 CF_ACR_EN | CF_ACR_SM_ALL) 300 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 301 CF_CACR_ICINVA | CF_CACR_EUSP) 302 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 303 CF_CACR_DEC | CF_CACR_DDCM_P | \ 304 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 305 306 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 307 CONFIG_SYS_INIT_RAM_SIZE - 12) 308 309 /*----------------------------------------------------------------------- 310 * Memory bank definitions 311 */ 312 /* 313 * CS0 - NOR Flash 16MB 314 * CS1 - Available 315 * CS2 - Available 316 * CS3 - Available 317 * CS4 - Available 318 * CS5 - Available 319 */ 320 321 /* Flash */ 322 #define CONFIG_SYS_CS0_BASE 0x00000000 323 #define CONFIG_SYS_CS0_MASK 0x000F0101 324 #define CONFIG_SYS_CS0_CTRL 0x00001D60 325 326 #endif /* _M54418TWR_H */ 327