1 /* 2 * Configuation settings for the Freescale MCF54418 TWR board. 3 * 4 * Copyright 2010-2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54418TWR_H 15 #define _M54418TWR_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54418TWR /* M54418TWR board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 #define CONFIG_BAUDRATE 115200 26 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 27 28 #undef CONFIG_WATCHDOG 29 30 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 31 32 /* 33 * BOOTP options 34 */ 35 #define CONFIG_BOOTP_BOOTFILESIZE 36 #define CONFIG_BOOTP_BOOTPATH 37 #define CONFIG_BOOTP_GATEWAY 38 #define CONFIG_BOOTP_HOSTNAME 39 40 /* Command line configuration */ 41 #undef CONFIG_CMD_DATE 42 #undef CONFIG_CMD_JFFS2 43 #undef CONFIG_CMD_UBI 44 #undef CONFIG_CMD_NAND 45 #define CONFIG_CMD_REGINFO 46 47 /* 48 * NAND FLASH 49 */ 50 #ifdef CONFIG_CMD_NAND 51 #define CONFIG_JFFS2_NAND 52 #define CONFIG_NAND_FSL_NFC 53 #define CONFIG_SYS_NAND_BASE 0xFC0FC000 54 #define CONFIG_SYS_MAX_NAND_DEVICE 1 55 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE 56 #define CONFIG_SYS_NAND_SELECT_DEVICE 57 #endif 58 59 /* Network configuration */ 60 #define CONFIG_MCFFEC 61 #ifdef CONFIG_MCFFEC 62 #define CONFIG_MII 1 63 #define CONFIG_MII_INIT 1 64 #define CONFIG_SYS_DISCOVER_PHY 65 #define CONFIG_SYS_RX_ETH_BUFFER 2 66 #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN 67 #define CONFIG_SYS_TX_ETH_BUFFER 2 68 #define CONFIG_HAS_ETH1 69 70 #define CONFIG_SYS_FEC0_PINMUX 0 71 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 72 #define CONFIG_SYS_FEC1_PINMUX 0 73 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE 74 #define MCFFEC_TOUT_LOOP 50000 75 #define CONFIG_SYS_FEC0_PHYADDR 0 76 #define CONFIG_SYS_FEC1_PHYADDR 1 77 78 #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ 79 80 #ifdef CONFIG_SYS_NAND_BOOT 81 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \ 82 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \ 83 "-(jffs2) console=ttyS0,115200" 84 #else 85 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \ 86 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \ 87 __stringify(CONFIG_IPADDR) " ip=" \ 88 __stringify(CONFIG_IPADDR) ":" \ 89 __stringify(CONFIG_SERVERIP)":" \ 90 __stringify(CONFIG_GATEWAYIP)": " \ 91 __stringify(CONFIG_NETMASK) \ 92 "::eth0:off:rw console=ttyS0,115200" 93 #endif 94 95 #define CONFIG_ETHPRIME "FEC0" 96 #define CONFIG_IPADDR 192.168.1.2 97 #define CONFIG_NETMASK 255.255.255.0 98 #define CONFIG_SERVERIP 192.168.1.1 99 #define CONFIG_GATEWAYIP 192.168.1.1 100 101 #define CONFIG_SYS_FEC_BUF_USE_SRAM 102 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 103 #ifndef CONFIG_SYS_DISCOVER_PHY 104 #define FECDUPLEX FULL 105 #define FECSPEED _100BASET 106 #define LINKSTATUS 1 107 #else 108 #define LINKSTATUS 0 109 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 110 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 111 #endif 112 #endif /* CONFIG_SYS_DISCOVER_PHY */ 113 #endif 114 115 #define CONFIG_HOSTNAME M54418TWR 116 117 #if defined(CONFIG_CF_SBF) 118 /* ST Micro serial flash */ 119 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 120 #define CONFIG_EXTRA_ENV_SETTINGS \ 121 "netdev=eth0\0" \ 122 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 123 "loadaddr=0x40010000\0" \ 124 "sbfhdr=sbfhdr.bin\0" \ 125 "uboot=u-boot.bin\0" \ 126 "load=tftp ${loadaddr} ${sbfhdr};" \ 127 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 128 "upd=run load; run prog\0" \ 129 "prog=sf probe 0:1 1000000 3;" \ 130 "sf erase 0 40000;" \ 131 "sf write ${loadaddr} 0 40000;" \ 132 "save\0" \ 133 "" 134 #elif defined(CONFIG_SYS_NAND_BOOT) 135 #define CONFIG_EXTRA_ENV_SETTINGS \ 136 "netdev=eth0\0" \ 137 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 138 "loadaddr=0x40010000\0" \ 139 "u-boot=u-boot.bin\0" \ 140 "load=tftp ${loadaddr} ${u-boot};\0" \ 141 "upd=run load; run prog\0" \ 142 "prog=nand device 0;" \ 143 "nand erase 0 40000;" \ 144 "nb_update ${loadaddr} ${filesize};" \ 145 "save\0" \ 146 "" 147 #else 148 #define CONFIG_SYS_UBOOT_END 0x3FFFF 149 #define CONFIG_EXTRA_ENV_SETTINGS \ 150 "netdev=eth0\0" \ 151 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 152 "loadaddr=40010000\0" \ 153 "u-boot=u-boot.bin\0" \ 154 "load=tftp ${loadaddr) ${u-boot}\0" \ 155 "upd=run load; run prog\0" \ 156 "prog=prot off mram" " ;" \ 157 "cp.b ${loadaddr} 0 ${filesize};" \ 158 "save\0" \ 159 "" 160 #endif 161 162 /* Realtime clock */ 163 #undef CONFIG_MCFRTC 164 #define CONFIG_RTC_MCFRRTC 165 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 166 167 /* Timer */ 168 #define CONFIG_MCFTMR 169 #undef CONFIG_MCFPIT 170 171 /* I2c */ 172 #undef CONFIG_SYS_FSL_I2C 173 #undef CONFIG_HARD_I2C /* I2C with hardware support */ 174 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 175 /* I2C speed and slave address */ 176 #define CONFIG_SYS_I2C_SPEED 80000 177 #define CONFIG_SYS_I2C_SLAVE 0x7F 178 #define CONFIG_SYS_I2C_OFFSET 0x58000 179 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 180 181 /* DSPI and Serial Flash */ 182 #define CONFIG_CF_SPI 183 #define CONFIG_CF_DSPI 184 #define CONFIG_SERIAL_FLASH 185 #define CONFIG_HARD_SPI 186 #define CONFIG_SYS_SBFHDR_SIZE 0x7 187 #ifdef CONFIG_CMD_SPI 188 189 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 190 DSPI_CTAR_PCSSCK_1CLK | \ 191 DSPI_CTAR_PASC(0) | \ 192 DSPI_CTAR_PDT(0) | \ 193 DSPI_CTAR_CSSCK(0) | \ 194 DSPI_CTAR_ASC(0) | \ 195 DSPI_CTAR_DT(1)) 196 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 197 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 198 #endif 199 200 /* Input, PCI, Flexbus, and VCO */ 201 #define CONFIG_EXTRA_CLOCK 202 203 #define CONFIG_PRAM 2048 /* 2048 KB */ 204 205 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 206 207 #if defined(CONFIG_CMD_KGDB) 208 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 209 #else 210 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 211 #endif 212 /* Print Buffer Size */ 213 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 214 sizeof(CONFIG_SYS_PROMPT) + 16) 215 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 216 /* Boot Argument Buffer Size */ 217 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 218 219 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 220 221 #define CONFIG_SYS_MBAR 0xFC000000 222 223 /* 224 * Low Level Configuration Settings 225 * (address mappings, register initial values, etc.) 226 * You should know what you are doing if you make changes here. 227 */ 228 229 /*----------------------------------------------------------------------- 230 * Definitions for initial stack pointer and data area (in DPRAM) 231 */ 232 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 233 /* End of used area in internal SRAM */ 234 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 235 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 236 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ 237 GENERATED_GBL_DATA_SIZE) - 32) 238 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 239 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 240 241 /*----------------------------------------------------------------------- 242 * Start addresses for the final memory configuration 243 * (Set up by the startup code) 244 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 245 */ 246 #define CONFIG_SYS_SDRAM_BASE 0x40000000 247 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 248 249 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) 250 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 251 #define CONFIG_SYS_DRAM_TEST 252 253 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) 254 #define CONFIG_SERIAL_BOOT 255 #endif 256 257 #if defined(CONFIG_SERIAL_BOOT) 258 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 259 #else 260 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 261 #endif 262 263 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 264 /* Reserve 256 kB for Monitor */ 265 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 266 /* Reserve 256 kB for malloc() */ 267 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 268 269 /* 270 * For booting Linux, the board info and command line data 271 * have to be in the first 8 MB of memory, since this is 272 * the maximum mapped by the Linux kernel during initialization ?? 273 */ 274 /* Initial Memory map for Linux */ 275 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 276 (CONFIG_SYS_SDRAM_SIZE << 20)) 277 278 /* Configuration for environment 279 * Environment is embedded in u-boot in the second sector of the flash 280 */ 281 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ 282 #define CONFIG_SYS_NO_FLASH 283 #define CONFIG_ENV_IS_IN_MRAM 1 284 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ 285 #define CONFIG_ENV_SIZE 0x1000 286 #endif 287 288 #if defined(CONFIG_CF_SBF) 289 #define CONFIG_SYS_NO_FLASH 290 #define CONFIG_ENV_IS_IN_SPI_FLASH 1 291 #define CONFIG_ENV_SPI_CS 1 292 #define CONFIG_ENV_OFFSET 0x40000 293 #define CONFIG_ENV_SIZE 0x2000 294 #define CONFIG_ENV_SECT_SIZE 0x10000 295 #endif 296 #if defined(CONFIG_SYS_NAND_BOOT) 297 #define CONFIG_SYS_NO_FLASH 298 #define CONFIG_ENV_IS_NOWHERE 299 #define CONFIG_ENV_OFFSET 0x80000 300 #define CONFIG_ENV_SIZE 0x20000 301 #define CONFIG_ENV_SECT_SIZE 0x20000 302 #endif 303 #undef CONFIG_ENV_OVERWRITE 304 305 /* FLASH organization */ 306 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 307 308 #undef CONFIG_SYS_FLASH_CFI 309 #ifdef CONFIG_SYS_FLASH_CFI 310 311 #define CONFIG_FLASH_CFI_DRIVER 1 312 /* Max size that the board might have */ 313 #define CONFIG_SYS_FLASH_SIZE 0x1000000 314 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 315 /* max number of memory banks */ 316 #define CONFIG_SYS_MAX_FLASH_BANKS 1 317 /* max number of sectors on one chip */ 318 #define CONFIG_SYS_MAX_FLASH_SECT 270 319 /* "Real" (hardware) sectors protection */ 320 #define CONFIG_SYS_FLASH_PROTECTION 321 #define CONFIG_SYS_FLASH_CHECKSUM 322 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 323 #else 324 /* max number of sectors on one chip */ 325 #define CONFIG_SYS_MAX_FLASH_SECT 270 326 /* max number of sectors on one chip */ 327 #define CONFIG_SYS_MAX_FLASH_BANKS 0 328 #endif 329 330 /* 331 * This is setting for JFFS2 support in u-boot. 332 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 333 */ 334 #ifdef CONFIG_CMD_JFFS2 335 #define CONFIG_JFFS2_DEV "nand0" 336 #define CONFIG_JFFS2_PART_OFFSET (0x800000) 337 #define CONFIG_CMD_MTDPARTS 338 #define CONFIG_MTD_DEVICE 339 #define MTDIDS_DEFAULT "nand0=m54418twr.nand" 340 341 #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \ 342 "7m(kernel)," \ 343 "-(rootfs)" 344 345 #endif 346 347 #ifdef CONFIG_CMD_UBI 348 #define CONFIG_CMD_MTDPARTS 349 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */ 350 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */ 351 #define CONFIG_RBTREE 352 #define MTDIDS_DEFAULT "nand0=NAND" 353 #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \ 354 "-(ubi)" 355 #endif 356 /* Cache Configuration */ 357 #define CONFIG_SYS_CACHELINE_SIZE 16 358 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 359 CONFIG_SYS_INIT_RAM_SIZE - 8) 360 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 361 CONFIG_SYS_INIT_RAM_SIZE - 4) 362 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 363 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 364 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 365 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 366 CF_ACR_EN | CF_ACR_SM_ALL) 367 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 368 CF_CACR_ICINVA | CF_CACR_EUSP) 369 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 370 CF_CACR_DEC | CF_CACR_DDCM_P | \ 371 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 372 373 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 374 CONFIG_SYS_INIT_RAM_SIZE - 12) 375 376 /*----------------------------------------------------------------------- 377 * Memory bank definitions 378 */ 379 /* 380 * CS0 - NOR Flash 16MB 381 * CS1 - Available 382 * CS2 - Available 383 * CS3 - Available 384 * CS4 - Available 385 * CS5 - Available 386 */ 387 388 /* Flash */ 389 #define CONFIG_SYS_CS0_BASE 0x00000000 390 #define CONFIG_SYS_CS0_MASK 0x000F0101 391 #define CONFIG_SYS_CS0_CTRL 0x00001D60 392 393 #endif /* _M54418TWR_H */ 394