1 /* 2 * Configuation settings for the Freescale MCF54418 TWR board. 3 * 4 * Copyright 2010-2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54418TWR_H 15 #define _M54418TWR_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54418TWR /* M54418TWR board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 26 27 #undef CONFIG_WATCHDOG 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 #define CONFIG_BOOTP_BOOTPATH 36 #define CONFIG_BOOTP_GATEWAY 37 #define CONFIG_BOOTP_HOSTNAME 38 39 /* Command line configuration */ 40 #undef CONFIG_CMD_DATE 41 #undef CONFIG_CMD_JFFS2 42 #undef CONFIG_CMD_NAND 43 #define CONFIG_CMD_REGINFO 44 45 /* 46 * NAND FLASH 47 */ 48 #ifdef CONFIG_CMD_NAND 49 #define CONFIG_JFFS2_NAND 50 #define CONFIG_NAND_FSL_NFC 51 #define CONFIG_SYS_NAND_BASE 0xFC0FC000 52 #define CONFIG_SYS_MAX_NAND_DEVICE 1 53 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE 54 #define CONFIG_SYS_NAND_SELECT_DEVICE 55 #endif 56 57 /* Network configuration */ 58 #define CONFIG_MCFFEC 59 #ifdef CONFIG_MCFFEC 60 #define CONFIG_MII 1 61 #define CONFIG_MII_INIT 1 62 #define CONFIG_SYS_DISCOVER_PHY 63 #define CONFIG_SYS_RX_ETH_BUFFER 2 64 #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN 65 #define CONFIG_SYS_TX_ETH_BUFFER 2 66 #define CONFIG_HAS_ETH1 67 68 #define CONFIG_SYS_FEC0_PINMUX 0 69 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 70 #define CONFIG_SYS_FEC1_PINMUX 0 71 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE 72 #define MCFFEC_TOUT_LOOP 50000 73 #define CONFIG_SYS_FEC0_PHYADDR 0 74 #define CONFIG_SYS_FEC1_PHYADDR 1 75 76 77 #ifdef CONFIG_SYS_NAND_BOOT 78 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \ 79 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \ 80 "-(jffs2) console=ttyS0,115200" 81 #else 82 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \ 83 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \ 84 __stringify(CONFIG_IPADDR) " ip=" \ 85 __stringify(CONFIG_IPADDR) ":" \ 86 __stringify(CONFIG_SERVERIP)":" \ 87 __stringify(CONFIG_GATEWAYIP)": " \ 88 __stringify(CONFIG_NETMASK) \ 89 "::eth0:off:rw console=ttyS0,115200" 90 #endif 91 92 #define CONFIG_ETHPRIME "FEC0" 93 #define CONFIG_IPADDR 192.168.1.2 94 #define CONFIG_NETMASK 255.255.255.0 95 #define CONFIG_SERVERIP 192.168.1.1 96 #define CONFIG_GATEWAYIP 192.168.1.1 97 98 #define CONFIG_SYS_FEC_BUF_USE_SRAM 99 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 100 #ifndef CONFIG_SYS_DISCOVER_PHY 101 #define FECDUPLEX FULL 102 #define FECSPEED _100BASET 103 #define LINKSTATUS 1 104 #else 105 #define LINKSTATUS 0 106 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 107 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 108 #endif 109 #endif /* CONFIG_SYS_DISCOVER_PHY */ 110 #endif 111 112 #define CONFIG_HOSTNAME M54418TWR 113 114 #if defined(CONFIG_CF_SBF) 115 /* ST Micro serial flash */ 116 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 117 #define CONFIG_EXTRA_ENV_SETTINGS \ 118 "netdev=eth0\0" \ 119 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 120 "loadaddr=0x40010000\0" \ 121 "sbfhdr=sbfhdr.bin\0" \ 122 "uboot=u-boot.bin\0" \ 123 "load=tftp ${loadaddr} ${sbfhdr};" \ 124 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 125 "upd=run load; run prog\0" \ 126 "prog=sf probe 0:1 1000000 3;" \ 127 "sf erase 0 40000;" \ 128 "sf write ${loadaddr} 0 40000;" \ 129 "save\0" \ 130 "" 131 #elif defined(CONFIG_SYS_NAND_BOOT) 132 #define CONFIG_EXTRA_ENV_SETTINGS \ 133 "netdev=eth0\0" \ 134 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 135 "loadaddr=0x40010000\0" \ 136 "u-boot=u-boot.bin\0" \ 137 "load=tftp ${loadaddr} ${u-boot};\0" \ 138 "upd=run load; run prog\0" \ 139 "prog=nand device 0;" \ 140 "nand erase 0 40000;" \ 141 "nb_update ${loadaddr} ${filesize};" \ 142 "save\0" \ 143 "" 144 #else 145 #define CONFIG_SYS_UBOOT_END 0x3FFFF 146 #define CONFIG_EXTRA_ENV_SETTINGS \ 147 "netdev=eth0\0" \ 148 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 149 "loadaddr=40010000\0" \ 150 "u-boot=u-boot.bin\0" \ 151 "load=tftp ${loadaddr) ${u-boot}\0" \ 152 "upd=run load; run prog\0" \ 153 "prog=prot off mram" " ;" \ 154 "cp.b ${loadaddr} 0 ${filesize};" \ 155 "save\0" \ 156 "" 157 #endif 158 159 /* Realtime clock */ 160 #undef CONFIG_MCFRTC 161 #define CONFIG_RTC_MCFRRTC 162 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 163 164 /* Timer */ 165 #define CONFIG_MCFTMR 166 #undef CONFIG_MCFPIT 167 168 /* I2c */ 169 #undef CONFIG_SYS_FSL_I2C 170 #undef CONFIG_HARD_I2C /* I2C with hardware support */ 171 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 172 /* I2C speed and slave address */ 173 #define CONFIG_SYS_I2C_SPEED 80000 174 #define CONFIG_SYS_I2C_SLAVE 0x7F 175 #define CONFIG_SYS_I2C_OFFSET 0x58000 176 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 177 178 /* DSPI and Serial Flash */ 179 #define CONFIG_CF_SPI 180 #define CONFIG_CF_DSPI 181 #define CONFIG_SERIAL_FLASH 182 #define CONFIG_HARD_SPI 183 #define CONFIG_SYS_SBFHDR_SIZE 0x7 184 #ifdef CONFIG_CMD_SPI 185 186 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 187 DSPI_CTAR_PCSSCK_1CLK | \ 188 DSPI_CTAR_PASC(0) | \ 189 DSPI_CTAR_PDT(0) | \ 190 DSPI_CTAR_CSSCK(0) | \ 191 DSPI_CTAR_ASC(0) | \ 192 DSPI_CTAR_DT(1)) 193 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 194 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 195 #endif 196 197 /* Input, PCI, Flexbus, and VCO */ 198 #define CONFIG_EXTRA_CLOCK 199 200 #define CONFIG_PRAM 2048 /* 2048 KB */ 201 202 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 203 204 #if defined(CONFIG_CMD_KGDB) 205 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 206 #else 207 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 208 #endif 209 /* Print Buffer Size */ 210 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 211 sizeof(CONFIG_SYS_PROMPT) + 16) 212 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 213 /* Boot Argument Buffer Size */ 214 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 215 216 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 217 218 #define CONFIG_SYS_MBAR 0xFC000000 219 220 /* 221 * Low Level Configuration Settings 222 * (address mappings, register initial values, etc.) 223 * You should know what you are doing if you make changes here. 224 */ 225 226 /*----------------------------------------------------------------------- 227 * Definitions for initial stack pointer and data area (in DPRAM) 228 */ 229 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 230 /* End of used area in internal SRAM */ 231 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 232 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 233 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ 234 GENERATED_GBL_DATA_SIZE) - 32) 235 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 236 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 237 238 /*----------------------------------------------------------------------- 239 * Start addresses for the final memory configuration 240 * (Set up by the startup code) 241 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 242 */ 243 #define CONFIG_SYS_SDRAM_BASE 0x40000000 244 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 245 246 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) 247 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 248 #define CONFIG_SYS_DRAM_TEST 249 250 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) 251 #define CONFIG_SERIAL_BOOT 252 #endif 253 254 #if defined(CONFIG_SERIAL_BOOT) 255 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 256 #else 257 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 258 #endif 259 260 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 261 /* Reserve 256 kB for Monitor */ 262 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 263 /* Reserve 256 kB for malloc() */ 264 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 265 266 /* 267 * For booting Linux, the board info and command line data 268 * have to be in the first 8 MB of memory, since this is 269 * the maximum mapped by the Linux kernel during initialization ?? 270 */ 271 /* Initial Memory map for Linux */ 272 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 273 (CONFIG_SYS_SDRAM_SIZE << 20)) 274 275 /* Configuration for environment 276 * Environment is embedded in u-boot in the second sector of the flash 277 */ 278 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ 279 #define CONFIG_ENV_IS_IN_MRAM 1 280 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ 281 #define CONFIG_ENV_SIZE 0x1000 282 #endif 283 284 #if defined(CONFIG_CF_SBF) 285 #define CONFIG_ENV_IS_IN_SPI_FLASH 1 286 #define CONFIG_ENV_SPI_CS 1 287 #define CONFIG_ENV_OFFSET 0x40000 288 #define CONFIG_ENV_SIZE 0x2000 289 #define CONFIG_ENV_SECT_SIZE 0x10000 290 #endif 291 #if defined(CONFIG_SYS_NAND_BOOT) 292 #define CONFIG_ENV_IS_NOWHERE 293 #define CONFIG_ENV_OFFSET 0x80000 294 #define CONFIG_ENV_SIZE 0x20000 295 #define CONFIG_ENV_SECT_SIZE 0x20000 296 #endif 297 #undef CONFIG_ENV_OVERWRITE 298 299 /* FLASH organization */ 300 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 301 302 #undef CONFIG_SYS_FLASH_CFI 303 #ifdef CONFIG_SYS_FLASH_CFI 304 305 #define CONFIG_FLASH_CFI_DRIVER 1 306 /* Max size that the board might have */ 307 #define CONFIG_SYS_FLASH_SIZE 0x1000000 308 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 309 /* max number of memory banks */ 310 #define CONFIG_SYS_MAX_FLASH_BANKS 1 311 /* max number of sectors on one chip */ 312 #define CONFIG_SYS_MAX_FLASH_SECT 270 313 /* "Real" (hardware) sectors protection */ 314 #define CONFIG_SYS_FLASH_PROTECTION 315 #define CONFIG_SYS_FLASH_CHECKSUM 316 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 317 #else 318 /* max number of sectors on one chip */ 319 #define CONFIG_SYS_MAX_FLASH_SECT 270 320 /* max number of sectors on one chip */ 321 #define CONFIG_SYS_MAX_FLASH_BANKS 0 322 #endif 323 324 /* 325 * This is setting for JFFS2 support in u-boot. 326 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 327 */ 328 #ifdef CONFIG_CMD_JFFS2 329 #define CONFIG_JFFS2_DEV "nand0" 330 #define CONFIG_JFFS2_PART_OFFSET (0x800000) 331 #define CONFIG_CMD_MTDPARTS 332 #define CONFIG_MTD_DEVICE 333 #define MTDIDS_DEFAULT "nand0=m54418twr.nand" 334 335 #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \ 336 "7m(kernel)," \ 337 "-(rootfs)" 338 339 #endif 340 341 #ifdef CONFIG_CMD_UBI 342 #define CONFIG_CMD_MTDPARTS 343 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */ 344 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */ 345 #define CONFIG_RBTREE 346 #define MTDIDS_DEFAULT "nand0=NAND" 347 #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \ 348 "-(ubi)" 349 #endif 350 /* Cache Configuration */ 351 #define CONFIG_SYS_CACHELINE_SIZE 16 352 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 353 CONFIG_SYS_INIT_RAM_SIZE - 8) 354 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 355 CONFIG_SYS_INIT_RAM_SIZE - 4) 356 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 357 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 358 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 359 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 360 CF_ACR_EN | CF_ACR_SM_ALL) 361 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 362 CF_CACR_ICINVA | CF_CACR_EUSP) 363 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 364 CF_CACR_DEC | CF_CACR_DDCM_P | \ 365 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 366 367 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 368 CONFIG_SYS_INIT_RAM_SIZE - 12) 369 370 /*----------------------------------------------------------------------- 371 * Memory bank definitions 372 */ 373 /* 374 * CS0 - NOR Flash 16MB 375 * CS1 - Available 376 * CS2 - Available 377 * CS3 - Available 378 * CS4 - Available 379 * CS5 - Available 380 */ 381 382 /* Flash */ 383 #define CONFIG_SYS_CS0_BASE 0x00000000 384 #define CONFIG_SYS_CS0_MASK 0x000F0101 385 #define CONFIG_SYS_CS0_CTRL 0x00001D60 386 387 #endif /* _M54418TWR_H */ 388