1 /* 2 * Configuation settings for the Freescale MCF54418 TWR board. 3 * 4 * Copyright 2010-2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54418TWR_H 15 #define _M54418TWR_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54418TWR /* M54418TWR board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 26 27 #undef CONFIG_WATCHDOG 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 #define CONFIG_BOOTP_BOOTPATH 36 #define CONFIG_BOOTP_GATEWAY 37 #define CONFIG_BOOTP_HOSTNAME 38 39 /* Command line configuration */ 40 #undef CONFIG_CMD_NAND 41 42 /* 43 * NAND FLASH 44 */ 45 #ifdef CONFIG_CMD_NAND 46 #define CONFIG_JFFS2_NAND 47 #define CONFIG_NAND_FSL_NFC 48 #define CONFIG_SYS_NAND_BASE 0xFC0FC000 49 #define CONFIG_SYS_MAX_NAND_DEVICE 1 50 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE 51 #define CONFIG_SYS_NAND_SELECT_DEVICE 52 #endif 53 54 /* Network configuration */ 55 #define CONFIG_MCFFEC 56 #ifdef CONFIG_MCFFEC 57 #define CONFIG_MII 1 58 #define CONFIG_MII_INIT 1 59 #define CONFIG_SYS_DISCOVER_PHY 60 #define CONFIG_SYS_RX_ETH_BUFFER 2 61 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 62 #define CONFIG_SYS_TX_ETH_BUFFER 2 63 #define CONFIG_HAS_ETH1 64 65 #define CONFIG_SYS_FEC0_PINMUX 0 66 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 67 #define CONFIG_SYS_FEC1_PINMUX 0 68 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE 69 #define MCFFEC_TOUT_LOOP 50000 70 #define CONFIG_SYS_FEC0_PHYADDR 0 71 #define CONFIG_SYS_FEC1_PHYADDR 1 72 73 74 #ifdef CONFIG_SYS_NAND_BOOT 75 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \ 76 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \ 77 "-(jffs2) console=ttyS0,115200" 78 #else 79 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \ 80 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \ 81 __stringify(CONFIG_IPADDR) " ip=" \ 82 __stringify(CONFIG_IPADDR) ":" \ 83 __stringify(CONFIG_SERVERIP)":" \ 84 __stringify(CONFIG_GATEWAYIP)": " \ 85 __stringify(CONFIG_NETMASK) \ 86 "::eth0:off:rw console=ttyS0,115200" 87 #endif 88 89 #define CONFIG_ETHPRIME "FEC0" 90 #define CONFIG_IPADDR 192.168.1.2 91 #define CONFIG_NETMASK 255.255.255.0 92 #define CONFIG_SERVERIP 192.168.1.1 93 #define CONFIG_GATEWAYIP 192.168.1.1 94 95 #define CONFIG_SYS_FEC_BUF_USE_SRAM 96 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 97 #ifndef CONFIG_SYS_DISCOVER_PHY 98 #define FECDUPLEX FULL 99 #define FECSPEED _100BASET 100 #define LINKSTATUS 1 101 #else 102 #define LINKSTATUS 0 103 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 104 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 105 #endif 106 #endif /* CONFIG_SYS_DISCOVER_PHY */ 107 #endif 108 109 #define CONFIG_HOSTNAME M54418TWR 110 111 #if defined(CONFIG_CF_SBF) 112 /* ST Micro serial flash */ 113 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 114 #define CONFIG_EXTRA_ENV_SETTINGS \ 115 "netdev=eth0\0" \ 116 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 117 "loadaddr=0x40010000\0" \ 118 "sbfhdr=sbfhdr.bin\0" \ 119 "uboot=u-boot.bin\0" \ 120 "load=tftp ${loadaddr} ${sbfhdr};" \ 121 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 122 "upd=run load; run prog\0" \ 123 "prog=sf probe 0:1 1000000 3;" \ 124 "sf erase 0 40000;" \ 125 "sf write ${loadaddr} 0 40000;" \ 126 "save\0" \ 127 "" 128 #elif defined(CONFIG_SYS_NAND_BOOT) 129 #define CONFIG_EXTRA_ENV_SETTINGS \ 130 "netdev=eth0\0" \ 131 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 132 "loadaddr=0x40010000\0" \ 133 "u-boot=u-boot.bin\0" \ 134 "load=tftp ${loadaddr} ${u-boot};\0" \ 135 "upd=run load; run prog\0" \ 136 "prog=nand device 0;" \ 137 "nand erase 0 40000;" \ 138 "nb_update ${loadaddr} ${filesize};" \ 139 "save\0" \ 140 "" 141 #else 142 #define CONFIG_SYS_UBOOT_END 0x3FFFF 143 #define CONFIG_EXTRA_ENV_SETTINGS \ 144 "netdev=eth0\0" \ 145 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 146 "loadaddr=40010000\0" \ 147 "u-boot=u-boot.bin\0" \ 148 "load=tftp ${loadaddr) ${u-boot}\0" \ 149 "upd=run load; run prog\0" \ 150 "prog=prot off mram" " ;" \ 151 "cp.b ${loadaddr} 0 ${filesize};" \ 152 "save\0" \ 153 "" 154 #endif 155 156 /* Realtime clock */ 157 #undef CONFIG_MCFRTC 158 #define CONFIG_RTC_MCFRRTC 159 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 160 161 /* Timer */ 162 #define CONFIG_MCFTMR 163 #undef CONFIG_MCFPIT 164 165 /* I2c */ 166 #undef CONFIG_SYS_FSL_I2C 167 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 168 /* I2C speed and slave address */ 169 #define CONFIG_SYS_I2C_SPEED 80000 170 #define CONFIG_SYS_I2C_SLAVE 0x7F 171 #define CONFIG_SYS_I2C_OFFSET 0x58000 172 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 173 174 /* DSPI and Serial Flash */ 175 #define CONFIG_CF_SPI 176 #define CONFIG_CF_DSPI 177 #define CONFIG_SERIAL_FLASH 178 #define CONFIG_HARD_SPI 179 #define CONFIG_SYS_SBFHDR_SIZE 0x7 180 #ifdef CONFIG_CMD_SPI 181 182 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 183 DSPI_CTAR_PCSSCK_1CLK | \ 184 DSPI_CTAR_PASC(0) | \ 185 DSPI_CTAR_PDT(0) | \ 186 DSPI_CTAR_CSSCK(0) | \ 187 DSPI_CTAR_ASC(0) | \ 188 DSPI_CTAR_DT(1)) 189 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 190 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 191 #endif 192 193 /* Input, PCI, Flexbus, and VCO */ 194 #define CONFIG_EXTRA_CLOCK 195 196 #define CONFIG_PRAM 2048 /* 2048 KB */ 197 198 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 199 200 #if defined(CONFIG_CMD_KGDB) 201 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 202 #else 203 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 204 #endif 205 /* Print Buffer Size */ 206 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 207 sizeof(CONFIG_SYS_PROMPT) + 16) 208 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 209 /* Boot Argument Buffer Size */ 210 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 211 212 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 213 214 #define CONFIG_SYS_MBAR 0xFC000000 215 216 /* 217 * Low Level Configuration Settings 218 * (address mappings, register initial values, etc.) 219 * You should know what you are doing if you make changes here. 220 */ 221 222 /*----------------------------------------------------------------------- 223 * Definitions for initial stack pointer and data area (in DPRAM) 224 */ 225 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 226 /* End of used area in internal SRAM */ 227 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 228 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 229 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ 230 GENERATED_GBL_DATA_SIZE) - 32) 231 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 232 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 233 234 /*----------------------------------------------------------------------- 235 * Start addresses for the final memory configuration 236 * (Set up by the startup code) 237 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 238 */ 239 #define CONFIG_SYS_SDRAM_BASE 0x40000000 240 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 241 242 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) 243 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 244 #define CONFIG_SYS_DRAM_TEST 245 246 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) 247 #define CONFIG_SERIAL_BOOT 248 #endif 249 250 #if defined(CONFIG_SERIAL_BOOT) 251 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 252 #else 253 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 254 #endif 255 256 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 257 /* Reserve 256 kB for Monitor */ 258 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 259 /* Reserve 256 kB for malloc() */ 260 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 261 262 /* 263 * For booting Linux, the board info and command line data 264 * have to be in the first 8 MB of memory, since this is 265 * the maximum mapped by the Linux kernel during initialization ?? 266 */ 267 /* Initial Memory map for Linux */ 268 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 269 (CONFIG_SYS_SDRAM_SIZE << 20)) 270 271 /* Configuration for environment 272 * Environment is embedded in u-boot in the second sector of the flash 273 */ 274 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ 275 #define CONFIG_ENV_IS_IN_MRAM 1 276 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ 277 #define CONFIG_ENV_SIZE 0x1000 278 #endif 279 280 #if defined(CONFIG_CF_SBF) 281 #define CONFIG_ENV_IS_IN_SPI_FLASH 1 282 #define CONFIG_ENV_SPI_CS 1 283 #define CONFIG_ENV_OFFSET 0x40000 284 #define CONFIG_ENV_SIZE 0x2000 285 #define CONFIG_ENV_SECT_SIZE 0x10000 286 #endif 287 #if defined(CONFIG_SYS_NAND_BOOT) 288 #define CONFIG_ENV_IS_NOWHERE 289 #define CONFIG_ENV_OFFSET 0x80000 290 #define CONFIG_ENV_SIZE 0x20000 291 #define CONFIG_ENV_SECT_SIZE 0x20000 292 #endif 293 #undef CONFIG_ENV_OVERWRITE 294 295 /* FLASH organization */ 296 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 297 298 #undef CONFIG_SYS_FLASH_CFI 299 #ifdef CONFIG_SYS_FLASH_CFI 300 301 #define CONFIG_FLASH_CFI_DRIVER 1 302 /* Max size that the board might have */ 303 #define CONFIG_SYS_FLASH_SIZE 0x1000000 304 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 305 /* max number of memory banks */ 306 #define CONFIG_SYS_MAX_FLASH_BANKS 1 307 /* max number of sectors on one chip */ 308 #define CONFIG_SYS_MAX_FLASH_SECT 270 309 /* "Real" (hardware) sectors protection */ 310 #define CONFIG_SYS_FLASH_PROTECTION 311 #define CONFIG_SYS_FLASH_CHECKSUM 312 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 313 #else 314 /* max number of sectors on one chip */ 315 #define CONFIG_SYS_MAX_FLASH_SECT 270 316 /* max number of sectors on one chip */ 317 #define CONFIG_SYS_MAX_FLASH_BANKS 0 318 #endif 319 320 /* 321 * This is setting for JFFS2 support in u-boot. 322 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 323 */ 324 #ifdef CONFIG_CMD_JFFS2 325 #define CONFIG_JFFS2_DEV "nand0" 326 #define CONFIG_JFFS2_PART_OFFSET (0x800000) 327 #define CONFIG_MTD_DEVICE 328 #define MTDIDS_DEFAULT "nand0=m54418twr.nand" 329 330 #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \ 331 "7m(kernel)," \ 332 "-(rootfs)" 333 334 #endif 335 336 #ifdef CONFIG_CMD_UBI 337 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */ 338 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */ 339 #define MTDIDS_DEFAULT "nand0=NAND" 340 #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \ 341 "-(ubi)" 342 #endif 343 /* Cache Configuration */ 344 #define CONFIG_SYS_CACHELINE_SIZE 16 345 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 346 CONFIG_SYS_INIT_RAM_SIZE - 8) 347 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 348 CONFIG_SYS_INIT_RAM_SIZE - 4) 349 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 350 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 351 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 352 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 353 CF_ACR_EN | CF_ACR_SM_ALL) 354 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 355 CF_CACR_ICINVA | CF_CACR_EUSP) 356 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 357 CF_CACR_DEC | CF_CACR_DDCM_P | \ 358 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 359 360 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 361 CONFIG_SYS_INIT_RAM_SIZE - 12) 362 363 /*----------------------------------------------------------------------- 364 * Memory bank definitions 365 */ 366 /* 367 * CS0 - NOR Flash 16MB 368 * CS1 - Available 369 * CS2 - Available 370 * CS3 - Available 371 * CS4 - Available 372 * CS5 - Available 373 */ 374 375 /* Flash */ 376 #define CONFIG_SYS_CS0_BASE 0x00000000 377 #define CONFIG_SYS_CS0_MASK 0x000F0101 378 #define CONFIG_SYS_CS0_CTRL 0x00001D60 379 380 #endif /* _M54418TWR_H */ 381