1 /* 2 * Configuation settings for the Freescale MCF54418 TWR board. 3 * 4 * Copyright 2010-2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54418TWR_H 15 #define _M54418TWR_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54418TWR /* M54418TWR board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 26 27 #undef CONFIG_WATCHDOG 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 #define CONFIG_BOOTP_BOOTPATH 36 #define CONFIG_BOOTP_GATEWAY 37 #define CONFIG_BOOTP_HOSTNAME 38 39 /* 40 * NAND FLASH 41 */ 42 #ifdef CONFIG_CMD_NAND 43 #define CONFIG_JFFS2_NAND 44 #define CONFIG_NAND_FSL_NFC 45 #define CONFIG_SYS_NAND_BASE 0xFC0FC000 46 #define CONFIG_SYS_MAX_NAND_DEVICE 1 47 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE 48 #define CONFIG_SYS_NAND_SELECT_DEVICE 49 #endif 50 51 /* Network configuration */ 52 #define CONFIG_MCFFEC 53 #ifdef CONFIG_MCFFEC 54 #define CONFIG_MII 1 55 #define CONFIG_MII_INIT 1 56 #define CONFIG_SYS_DISCOVER_PHY 57 #define CONFIG_SYS_RX_ETH_BUFFER 2 58 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 59 #define CONFIG_SYS_TX_ETH_BUFFER 2 60 #define CONFIG_HAS_ETH1 61 62 #define CONFIG_SYS_FEC0_PINMUX 0 63 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 64 #define CONFIG_SYS_FEC1_PINMUX 0 65 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE 66 #define MCFFEC_TOUT_LOOP 50000 67 #define CONFIG_SYS_FEC0_PHYADDR 0 68 #define CONFIG_SYS_FEC1_PHYADDR 1 69 70 #define CONFIG_ETHPRIME "FEC0" 71 #define CONFIG_IPADDR 192.168.1.2 72 #define CONFIG_NETMASK 255.255.255.0 73 #define CONFIG_SERVERIP 192.168.1.1 74 #define CONFIG_GATEWAYIP 192.168.1.1 75 76 #define CONFIG_SYS_FEC_BUF_USE_SRAM 77 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 78 #ifndef CONFIG_SYS_DISCOVER_PHY 79 #define FECDUPLEX FULL 80 #define FECSPEED _100BASET 81 #define LINKSTATUS 1 82 #else 83 #define LINKSTATUS 0 84 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 85 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 86 #endif 87 #endif /* CONFIG_SYS_DISCOVER_PHY */ 88 #endif 89 90 #define CONFIG_HOSTNAME M54418TWR 91 92 #if defined(CONFIG_CF_SBF) 93 /* ST Micro serial flash */ 94 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 95 #define CONFIG_EXTRA_ENV_SETTINGS \ 96 "netdev=eth0\0" \ 97 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 98 "loadaddr=0x40010000\0" \ 99 "sbfhdr=sbfhdr.bin\0" \ 100 "uboot=u-boot.bin\0" \ 101 "load=tftp ${loadaddr} ${sbfhdr};" \ 102 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 103 "upd=run load; run prog\0" \ 104 "prog=sf probe 0:1 1000000 3;" \ 105 "sf erase 0 40000;" \ 106 "sf write ${loadaddr} 0 40000;" \ 107 "save\0" \ 108 "" 109 #elif defined(CONFIG_SYS_NAND_BOOT) 110 #define CONFIG_EXTRA_ENV_SETTINGS \ 111 "netdev=eth0\0" \ 112 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 113 "loadaddr=0x40010000\0" \ 114 "u-boot=u-boot.bin\0" \ 115 "load=tftp ${loadaddr} ${u-boot};\0" \ 116 "upd=run load; run prog\0" \ 117 "prog=nand device 0;" \ 118 "nand erase 0 40000;" \ 119 "nb_update ${loadaddr} ${filesize};" \ 120 "save\0" \ 121 "" 122 #else 123 #define CONFIG_SYS_UBOOT_END 0x3FFFF 124 #define CONFIG_EXTRA_ENV_SETTINGS \ 125 "netdev=eth0\0" \ 126 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 127 "loadaddr=40010000\0" \ 128 "u-boot=u-boot.bin\0" \ 129 "load=tftp ${loadaddr) ${u-boot}\0" \ 130 "upd=run load; run prog\0" \ 131 "prog=prot off mram" " ;" \ 132 "cp.b ${loadaddr} 0 ${filesize};" \ 133 "save\0" \ 134 "" 135 #endif 136 137 /* Realtime clock */ 138 #undef CONFIG_MCFRTC 139 #define CONFIG_RTC_MCFRRTC 140 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 141 142 /* Timer */ 143 #define CONFIG_MCFTMR 144 #undef CONFIG_MCFPIT 145 146 /* I2c */ 147 #undef CONFIG_SYS_FSL_I2C 148 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 149 /* I2C speed and slave address */ 150 #define CONFIG_SYS_I2C_SPEED 80000 151 #define CONFIG_SYS_I2C_SLAVE 0x7F 152 #define CONFIG_SYS_I2C_OFFSET 0x58000 153 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 154 155 /* DSPI and Serial Flash */ 156 #define CONFIG_CF_SPI 157 #define CONFIG_CF_DSPI 158 #define CONFIG_SERIAL_FLASH 159 #define CONFIG_HARD_SPI 160 #define CONFIG_SYS_SBFHDR_SIZE 0x7 161 #ifdef CONFIG_CMD_SPI 162 163 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 164 DSPI_CTAR_PCSSCK_1CLK | \ 165 DSPI_CTAR_PASC(0) | \ 166 DSPI_CTAR_PDT(0) | \ 167 DSPI_CTAR_CSSCK(0) | \ 168 DSPI_CTAR_ASC(0) | \ 169 DSPI_CTAR_DT(1)) 170 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 171 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 172 #endif 173 174 /* Input, PCI, Flexbus, and VCO */ 175 #define CONFIG_EXTRA_CLOCK 176 177 #define CONFIG_PRAM 2048 /* 2048 KB */ 178 179 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 180 181 #if defined(CONFIG_CMD_KGDB) 182 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 183 #else 184 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 185 #endif 186 /* Print Buffer Size */ 187 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 188 sizeof(CONFIG_SYS_PROMPT) + 16) 189 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 190 /* Boot Argument Buffer Size */ 191 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 192 193 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 194 195 #define CONFIG_SYS_MBAR 0xFC000000 196 197 /* 198 * Low Level Configuration Settings 199 * (address mappings, register initial values, etc.) 200 * You should know what you are doing if you make changes here. 201 */ 202 203 /*----------------------------------------------------------------------- 204 * Definitions for initial stack pointer and data area (in DPRAM) 205 */ 206 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 207 /* End of used area in internal SRAM */ 208 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 209 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 210 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ 211 GENERATED_GBL_DATA_SIZE) - 32) 212 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 213 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 214 215 /*----------------------------------------------------------------------- 216 * Start addresses for the final memory configuration 217 * (Set up by the startup code) 218 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 219 */ 220 #define CONFIG_SYS_SDRAM_BASE 0x40000000 221 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 222 223 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) 224 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 225 #define CONFIG_SYS_DRAM_TEST 226 227 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) 228 #define CONFIG_SERIAL_BOOT 229 #endif 230 231 #if defined(CONFIG_SERIAL_BOOT) 232 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 233 #else 234 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 235 #endif 236 237 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 238 /* Reserve 256 kB for Monitor */ 239 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 240 /* Reserve 256 kB for malloc() */ 241 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 242 243 /* 244 * For booting Linux, the board info and command line data 245 * have to be in the first 8 MB of memory, since this is 246 * the maximum mapped by the Linux kernel during initialization ?? 247 */ 248 /* Initial Memory map for Linux */ 249 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 250 (CONFIG_SYS_SDRAM_SIZE << 20)) 251 252 /* Configuration for environment 253 * Environment is embedded in u-boot in the second sector of the flash 254 */ 255 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ 256 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ 257 #define CONFIG_ENV_SIZE 0x1000 258 #endif 259 260 #if defined(CONFIG_CF_SBF) 261 #define CONFIG_ENV_SPI_CS 1 262 #define CONFIG_ENV_OFFSET 0x40000 263 #define CONFIG_ENV_SIZE 0x2000 264 #define CONFIG_ENV_SECT_SIZE 0x10000 265 #endif 266 #if defined(CONFIG_SYS_NAND_BOOT) 267 #define CONFIG_ENV_OFFSET 0x80000 268 #define CONFIG_ENV_SIZE 0x20000 269 #define CONFIG_ENV_SECT_SIZE 0x20000 270 #endif 271 #undef CONFIG_ENV_OVERWRITE 272 273 /* FLASH organization */ 274 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 275 276 #undef CONFIG_SYS_FLASH_CFI 277 #ifdef CONFIG_SYS_FLASH_CFI 278 279 #define CONFIG_FLASH_CFI_DRIVER 1 280 /* Max size that the board might have */ 281 #define CONFIG_SYS_FLASH_SIZE 0x1000000 282 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 283 /* max number of memory banks */ 284 #define CONFIG_SYS_MAX_FLASH_BANKS 1 285 /* max number of sectors on one chip */ 286 #define CONFIG_SYS_MAX_FLASH_SECT 270 287 /* "Real" (hardware) sectors protection */ 288 #define CONFIG_SYS_FLASH_PROTECTION 289 #define CONFIG_SYS_FLASH_CHECKSUM 290 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 291 #else 292 /* max number of sectors on one chip */ 293 #define CONFIG_SYS_MAX_FLASH_SECT 270 294 /* max number of sectors on one chip */ 295 #define CONFIG_SYS_MAX_FLASH_BANKS 0 296 #endif 297 298 /* 299 * This is setting for JFFS2 support in u-boot. 300 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 301 */ 302 #ifdef CONFIG_CMD_JFFS2 303 #define CONFIG_JFFS2_DEV "nand0" 304 #define CONFIG_JFFS2_PART_OFFSET (0x800000) 305 #define CONFIG_MTD_DEVICE 306 #define MTDIDS_DEFAULT "nand0=m54418twr.nand" 307 308 #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \ 309 "7m(kernel)," \ 310 "-(rootfs)" 311 312 #endif 313 314 #ifdef CONFIG_CMD_UBI 315 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */ 316 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */ 317 #define MTDIDS_DEFAULT "nand0=NAND" 318 #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \ 319 "-(ubi)" 320 #endif 321 /* Cache Configuration */ 322 #define CONFIG_SYS_CACHELINE_SIZE 16 323 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 324 CONFIG_SYS_INIT_RAM_SIZE - 8) 325 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 326 CONFIG_SYS_INIT_RAM_SIZE - 4) 327 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 328 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 329 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 330 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 331 CF_ACR_EN | CF_ACR_SM_ALL) 332 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 333 CF_CACR_ICINVA | CF_CACR_EUSP) 334 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 335 CF_CACR_DEC | CF_CACR_DDCM_P | \ 336 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 337 338 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 339 CONFIG_SYS_INIT_RAM_SIZE - 12) 340 341 /*----------------------------------------------------------------------- 342 * Memory bank definitions 343 */ 344 /* 345 * CS0 - NOR Flash 16MB 346 * CS1 - Available 347 * CS2 - Available 348 * CS3 - Available 349 * CS4 - Available 350 * CS5 - Available 351 */ 352 353 /* Flash */ 354 #define CONFIG_SYS_CS0_BASE 0x00000000 355 #define CONFIG_SYS_CS0_MASK 0x000F0101 356 #define CONFIG_SYS_CS0_CTRL 0x00001D60 357 358 #endif /* _M54418TWR_H */ 359