1 /* 2 * Configuation settings for the Freescale MCF54418 TWR board. 3 * 4 * Copyright 2010-2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54418TWR_H 15 #define _M54418TWR_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_MCF5441x /* define processor family */ 22 #define CONFIG_M54418 /* define processor type */ 23 #define CONFIG_M54418TWR /* M54418TWR board */ 24 25 #define CONFIG_MCFUART 26 #define CONFIG_SYS_UART_PORT (0) 27 #define CONFIG_BAUDRATE 115200 28 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 29 30 #undef CONFIG_WATCHDOG 31 32 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 33 34 /* 35 * BOOTP options 36 */ 37 #define CONFIG_BOOTP_BOOTFILESIZE 38 #define CONFIG_BOOTP_BOOTPATH 39 #define CONFIG_BOOTP_GATEWAY 40 #define CONFIG_BOOTP_HOSTNAME 41 42 /* Command line configuration */ 43 #include <config_cmd_default.h> 44 45 #define CONFIG_CMD_BOOTD 46 #define CONFIG_CMD_CACHE 47 #undef CONFIG_CMD_DATE 48 #define CONFIG_CMD_DHCP 49 #define CONFIG_CMD_ELF 50 #undef CONFIG_CMD_FLASH 51 #undef CONFIG_CMD_I2C 52 #undef CONFIG_CMD_JFFS2 53 #undef CONFIG_CMD_UBI 54 #define CONFIG_CMD_MEMORY 55 #define CONFIG_CMD_MISC 56 #define CONFIG_CMD_MII 57 #undef CONFIG_CMD_NAND 58 #undef CONFIG_CMD_NAND_YAFFS 59 #define CONFIG_CMD_NET 60 #define CONFIG_CMD_NFS 61 #define CONFIG_CMD_PING 62 #define CONFIG_CMD_REGINFO 63 #define CONFIG_CMD_SPI 64 #define CONFIG_CMD_SF 65 #undef CONFIG_CMD_IMLS 66 67 #undef CONFIG_CMD_LOADB 68 #undef CONFIG_CMD_LOADS 69 70 /* 71 * NAND FLASH 72 */ 73 #ifdef CONFIG_CMD_NAND 74 #define CONFIG_JFFS2_NAND 75 #define CONFIG_NAND_FSL_NFC 76 #define CONFIG_SYS_NAND_BASE 0xFC0FC000 77 #define CONFIG_SYS_MAX_NAND_DEVICE 1 78 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE 79 #define CONFIG_SYS_NAND_SELECT_DEVICE 80 #endif 81 82 /* Network configuration */ 83 #define CONFIG_MCFFEC 84 #ifdef CONFIG_MCFFEC 85 #define CONFIG_NET_MULTI 1 86 #define CONFIG_MII 1 87 #define CONFIG_MII_INIT 1 88 #define CONFIG_SYS_DISCOVER_PHY 89 #define CONFIG_SYS_RX_ETH_BUFFER 2 90 #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN 91 #define CONFIG_SYS_TX_ETH_BUFFER 2 92 #define CONFIG_HAS_ETH1 93 94 #define CONFIG_SYS_FEC0_PINMUX 0 95 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 96 #define CONFIG_SYS_FEC1_PINMUX 0 97 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE 98 #define MCFFEC_TOUT_LOOP 50000 99 #define CONFIG_SYS_FEC0_PHYADDR 0 100 #define CONFIG_SYS_FEC1_PHYADDR 1 101 102 #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ 103 104 #ifdef CONFIG_SYS_NAND_BOOT 105 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \ 106 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \ 107 "-(jffs2) console=ttyS0,115200" 108 #else 109 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \ 110 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \ 111 __stringify(CONFIG_IPADDR) " ip=" \ 112 __stringify(CONFIG_IPADDR) ":" \ 113 __stringify(CONFIG_SERVERIP)":" \ 114 __stringify(CONFIG_GATEWAYIP)": " \ 115 __stringify(CONFIG_NETMASK) \ 116 "::eth0:off:rw console=ttyS0,115200" 117 #endif 118 119 #define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 120 #define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 121 #define CONFIG_ETHPRIME "FEC0" 122 #define CONFIG_IPADDR 192.168.1.2 123 #define CONFIG_NETMASK 255.255.255.0 124 #define CONFIG_SERVERIP 192.168.1.1 125 #define CONFIG_GATEWAYIP 192.168.1.1 126 127 #define CONFIG_OVERWRITE_ETHADDR_ONCE 128 #define CONFIG_SYS_FEC_BUF_USE_SRAM 129 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 130 #ifndef CONFIG_SYS_DISCOVER_PHY 131 #define FECDUPLEX FULL 132 #define FECSPEED _100BASET 133 #define LINKSTATUS 1 134 #else 135 #define LINKSTATUS 0 136 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 137 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 138 #endif 139 #endif /* CONFIG_SYS_DISCOVER_PHY */ 140 #endif 141 142 #define CONFIG_HOSTNAME M54418TWR 143 144 #if defined(CONFIG_CF_SBF) 145 /* ST Micro serial flash */ 146 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 147 #define CONFIG_EXTRA_ENV_SETTINGS \ 148 "netdev=eth0\0" \ 149 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 150 "loadaddr=0x40010000\0" \ 151 "sbfhdr=sbfhdr.bin\0" \ 152 "uboot=u-boot.bin\0" \ 153 "load=tftp ${loadaddr} ${sbfhdr};" \ 154 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 155 "upd=run load; run prog\0" \ 156 "prog=sf probe 0:1 1000000 3;" \ 157 "sf erase 0 40000;" \ 158 "sf write ${loadaddr} 0 40000;" \ 159 "save\0" \ 160 "" 161 #elif defined(CONFIG_SYS_NAND_BOOT) 162 #define CONFIG_EXTRA_ENV_SETTINGS \ 163 "netdev=eth0\0" \ 164 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 165 "loadaddr=0x40010000\0" \ 166 "u-boot=u-boot.bin\0" \ 167 "load=tftp ${loadaddr} ${u-boot};\0" \ 168 "upd=run load; run prog\0" \ 169 "prog=nand device 0;" \ 170 "nand erase 0 40000;" \ 171 "nb_update ${loadaddr} ${filesize};" \ 172 "save\0" \ 173 "" 174 #else 175 #define CONFIG_SYS_UBOOT_END 0x3FFFF 176 #define CONFIG_EXTRA_ENV_SETTINGS \ 177 "netdev=eth0\0" \ 178 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 179 "loadaddr=40010000\0" \ 180 "u-boot=u-boot.bin\0" \ 181 "load=tftp ${loadaddr) ${u-boot}\0" \ 182 "upd=run load; run prog\0" \ 183 "prog=prot off mram" " ;" \ 184 "cp.b ${loadaddr} 0 ${filesize};" \ 185 "save\0" \ 186 "" 187 #endif 188 189 /* Realtime clock */ 190 #undef CONFIG_MCFRTC 191 #define CONFIG_RTC_MCFRRTC 192 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 193 194 /* Timer */ 195 #define CONFIG_MCFTMR 196 #undef CONFIG_MCFPIT 197 198 /* I2c */ 199 #undef CONFIG_SYS_FSL_I2C 200 #undef CONFIG_HARD_I2C /* I2C with hardware support */ 201 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 202 /* I2C speed and slave address */ 203 #define CONFIG_SYS_I2C_SPEED 80000 204 #define CONFIG_SYS_I2C_SLAVE 0x7F 205 #define CONFIG_SYS_I2C_OFFSET 0x58000 206 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 207 208 /* DSPI and Serial Flash */ 209 #define CONFIG_CF_SPI 210 #define CONFIG_CF_DSPI 211 #define CONFIG_SERIAL_FLASH 212 #define CONFIG_HARD_SPI 213 #define CONFIG_SYS_SBFHDR_SIZE 0x7 214 #ifdef CONFIG_CMD_SPI 215 # define CONFIG_SPI_FLASH 216 # define CONFIG_SPI_FLASH_ATMEL 217 218 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 219 DSPI_CTAR_PCSSCK_1CLK | \ 220 DSPI_CTAR_PASC(0) | \ 221 DSPI_CTAR_PDT(0) | \ 222 DSPI_CTAR_CSSCK(0) | \ 223 DSPI_CTAR_ASC(0) | \ 224 DSPI_CTAR_DT(1)) 225 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 226 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 227 #endif 228 229 /* Input, PCI, Flexbus, and VCO */ 230 #define CONFIG_EXTRA_CLOCK 231 232 #define CONFIG_PRAM 2048 /* 2048 KB */ 233 234 /* HUSH */ 235 #define CONFIG_SYS_HUSH_PARSER 1 236 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 237 238 #define CONFIG_SYS_PROMPT "-> " 239 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 240 241 #if defined(CONFIG_CMD_KGDB) 242 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 243 #else 244 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 245 #endif 246 /* Print Buffer Size */ 247 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 248 sizeof(CONFIG_SYS_PROMPT) + 16) 249 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 250 /* Boot Argument Buffer Size */ 251 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 252 253 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 254 255 #define CONFIG_SYS_MBAR 0xFC000000 256 257 /* 258 * Low Level Configuration Settings 259 * (address mappings, register initial values, etc.) 260 * You should know what you are doing if you make changes here. 261 */ 262 263 /*----------------------------------------------------------------------- 264 * Definitions for initial stack pointer and data area (in DPRAM) 265 */ 266 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 267 /* End of used area in internal SRAM */ 268 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 269 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 270 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ 271 GENERATED_GBL_DATA_SIZE) - 32) 272 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 273 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 274 275 /*----------------------------------------------------------------------- 276 * Start addresses for the final memory configuration 277 * (Set up by the startup code) 278 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 279 */ 280 #define CONFIG_SYS_SDRAM_BASE 0x40000000 281 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 282 283 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) 284 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 285 #define CONFIG_SYS_DRAM_TEST 286 287 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) 288 #define CONFIG_SERIAL_BOOT 289 #endif 290 291 #if defined(CONFIG_SERIAL_BOOT) 292 #define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400) 293 #else 294 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 295 #endif 296 297 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 298 /* Reserve 256 kB for Monitor */ 299 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 300 /* Reserve 256 kB for malloc() */ 301 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 302 303 /* 304 * For booting Linux, the board info and command line data 305 * have to be in the first 8 MB of memory, since this is 306 * the maximum mapped by the Linux kernel during initialization ?? 307 */ 308 /* Initial Memory map for Linux */ 309 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 310 (CONFIG_SYS_SDRAM_SIZE << 20)) 311 312 /* Configuration for environment 313 * Environment is embedded in u-boot in the second sector of the flash 314 */ 315 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ 316 #define CONFIG_SYS_NO_FLASH 317 #define CONFIG_ENV_IS_IN_MRAM 1 318 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ 319 #define CONFIG_ENV_SIZE 0x1000 320 #endif 321 322 #if defined(CONFIG_CF_SBF) 323 #define CONFIG_SYS_NO_FLASH 324 #define CONFIG_ENV_IS_IN_SPI_FLASH 1 325 #define CONFIG_ENV_SPI_CS 1 326 #define CONFIG_ENV_OFFSET 0x40000 327 #define CONFIG_ENV_SIZE 0x2000 328 #define CONFIG_ENV_SECT_SIZE 0x10000 329 #endif 330 #if defined(CONFIG_SYS_NAND_BOOT) 331 #define CONFIG_SYS_NO_FLASH 332 #define CONFIG_ENV_IS_NOWHERE 333 #define CONFIG_ENV_OFFSET 0x80000 334 #define CONFIG_ENV_SIZE 0x20000 335 #define CONFIG_ENV_SECT_SIZE 0x20000 336 #endif 337 #undef CONFIG_ENV_OVERWRITE 338 339 /* FLASH organization */ 340 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 341 342 #undef CONFIG_SYS_FLASH_CFI 343 #ifdef CONFIG_SYS_FLASH_CFI 344 345 #define CONFIG_FLASH_CFI_DRIVER 1 346 /* Max size that the board might have */ 347 #define CONFIG_SYS_FLASH_SIZE 0x1000000 348 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 349 /* max number of memory banks */ 350 #define CONFIG_SYS_MAX_FLASH_BANKS 1 351 /* max number of sectors on one chip */ 352 #define CONFIG_SYS_MAX_FLASH_SECT 270 353 /* "Real" (hardware) sectors protection */ 354 #define CONFIG_SYS_FLASH_PROTECTION 355 #define CONFIG_SYS_FLASH_CHECKSUM 356 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 357 #else 358 /* max number of sectors on one chip */ 359 #define CONFIG_SYS_MAX_FLASH_SECT 270 360 /* max number of sectors on one chip */ 361 #define CONFIG_SYS_MAX_FLASH_BANKS 0 362 #endif 363 364 /* 365 * This is setting for JFFS2 support in u-boot. 366 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 367 */ 368 #ifdef CONFIG_CMD_JFFS2 369 #define CONFIG_JFFS2_DEV "nand0" 370 #define CONFIG_JFFS2_PART_OFFSET (0x800000) 371 #define CONFIG_CMD_MTDPARTS 372 #define CONFIG_MTD_DEVICE 373 #define MTDIDS_DEFAULT "nand0=m54418twr.nand" 374 375 #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \ 376 "7m(kernel)," \ 377 "-(rootfs)" 378 379 #endif 380 381 #ifdef CONFIG_CMD_UBI 382 #define CONFIG_CMD_MTDPARTS 383 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */ 384 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */ 385 #define CONFIG_RBTREE 386 #define MTDIDS_DEFAULT "nand0=NAND" 387 #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \ 388 "-(ubi)" 389 #endif 390 /* Cache Configuration */ 391 #define CONFIG_SYS_CACHELINE_SIZE 16 392 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 393 CONFIG_SYS_INIT_RAM_SIZE - 8) 394 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 395 CONFIG_SYS_INIT_RAM_SIZE - 4) 396 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 397 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 398 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 399 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 400 CF_ACR_EN | CF_ACR_SM_ALL) 401 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 402 CF_CACR_ICINVA | CF_CACR_EUSP) 403 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 404 CF_CACR_DEC | CF_CACR_DDCM_P | \ 405 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 406 407 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 408 CONFIG_SYS_INIT_RAM_SIZE - 12) 409 410 /*----------------------------------------------------------------------- 411 * Memory bank definitions 412 */ 413 /* 414 * CS0 - NOR Flash 16MB 415 * CS1 - Available 416 * CS2 - Available 417 * CS3 - Available 418 * CS4 - Available 419 * CS5 - Available 420 */ 421 422 /* Flash */ 423 #define CONFIG_SYS_CS0_BASE 0x00000000 424 #define CONFIG_SYS_CS0_MASK 0x000F0101 425 #define CONFIG_SYS_CS0_CTRL 0x00001D60 426 427 #endif /* _M54418TWR_H */ 428