1 /* 2 * Configuation settings for the Freescale MCF54418 TWR board. 3 * 4 * Copyright 2010-2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54418TWR_H 15 #define _M54418TWR_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54418TWR /* M54418TWR board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 26 27 #undef CONFIG_WATCHDOG 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 #define CONFIG_BOOTP_BOOTPATH 36 #define CONFIG_BOOTP_GATEWAY 37 #define CONFIG_BOOTP_HOSTNAME 38 39 /* Command line configuration */ 40 #undef CONFIG_CMD_JFFS2 41 #undef CONFIG_CMD_NAND 42 #define CONFIG_CMD_REGINFO 43 44 /* 45 * NAND FLASH 46 */ 47 #ifdef CONFIG_CMD_NAND 48 #define CONFIG_JFFS2_NAND 49 #define CONFIG_NAND_FSL_NFC 50 #define CONFIG_SYS_NAND_BASE 0xFC0FC000 51 #define CONFIG_SYS_MAX_NAND_DEVICE 1 52 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE 53 #define CONFIG_SYS_NAND_SELECT_DEVICE 54 #endif 55 56 /* Network configuration */ 57 #define CONFIG_MCFFEC 58 #ifdef CONFIG_MCFFEC 59 #define CONFIG_MII 1 60 #define CONFIG_MII_INIT 1 61 #define CONFIG_SYS_DISCOVER_PHY 62 #define CONFIG_SYS_RX_ETH_BUFFER 2 63 #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN 64 #define CONFIG_SYS_TX_ETH_BUFFER 2 65 #define CONFIG_HAS_ETH1 66 67 #define CONFIG_SYS_FEC0_PINMUX 0 68 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 69 #define CONFIG_SYS_FEC1_PINMUX 0 70 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE 71 #define MCFFEC_TOUT_LOOP 50000 72 #define CONFIG_SYS_FEC0_PHYADDR 0 73 #define CONFIG_SYS_FEC1_PHYADDR 1 74 75 76 #ifdef CONFIG_SYS_NAND_BOOT 77 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \ 78 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \ 79 "-(jffs2) console=ttyS0,115200" 80 #else 81 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \ 82 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \ 83 __stringify(CONFIG_IPADDR) " ip=" \ 84 __stringify(CONFIG_IPADDR) ":" \ 85 __stringify(CONFIG_SERVERIP)":" \ 86 __stringify(CONFIG_GATEWAYIP)": " \ 87 __stringify(CONFIG_NETMASK) \ 88 "::eth0:off:rw console=ttyS0,115200" 89 #endif 90 91 #define CONFIG_ETHPRIME "FEC0" 92 #define CONFIG_IPADDR 192.168.1.2 93 #define CONFIG_NETMASK 255.255.255.0 94 #define CONFIG_SERVERIP 192.168.1.1 95 #define CONFIG_GATEWAYIP 192.168.1.1 96 97 #define CONFIG_SYS_FEC_BUF_USE_SRAM 98 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 99 #ifndef CONFIG_SYS_DISCOVER_PHY 100 #define FECDUPLEX FULL 101 #define FECSPEED _100BASET 102 #define LINKSTATUS 1 103 #else 104 #define LINKSTATUS 0 105 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 106 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 107 #endif 108 #endif /* CONFIG_SYS_DISCOVER_PHY */ 109 #endif 110 111 #define CONFIG_HOSTNAME M54418TWR 112 113 #if defined(CONFIG_CF_SBF) 114 /* ST Micro serial flash */ 115 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 116 #define CONFIG_EXTRA_ENV_SETTINGS \ 117 "netdev=eth0\0" \ 118 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 119 "loadaddr=0x40010000\0" \ 120 "sbfhdr=sbfhdr.bin\0" \ 121 "uboot=u-boot.bin\0" \ 122 "load=tftp ${loadaddr} ${sbfhdr};" \ 123 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 124 "upd=run load; run prog\0" \ 125 "prog=sf probe 0:1 1000000 3;" \ 126 "sf erase 0 40000;" \ 127 "sf write ${loadaddr} 0 40000;" \ 128 "save\0" \ 129 "" 130 #elif defined(CONFIG_SYS_NAND_BOOT) 131 #define CONFIG_EXTRA_ENV_SETTINGS \ 132 "netdev=eth0\0" \ 133 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 134 "loadaddr=0x40010000\0" \ 135 "u-boot=u-boot.bin\0" \ 136 "load=tftp ${loadaddr} ${u-boot};\0" \ 137 "upd=run load; run prog\0" \ 138 "prog=nand device 0;" \ 139 "nand erase 0 40000;" \ 140 "nb_update ${loadaddr} ${filesize};" \ 141 "save\0" \ 142 "" 143 #else 144 #define CONFIG_SYS_UBOOT_END 0x3FFFF 145 #define CONFIG_EXTRA_ENV_SETTINGS \ 146 "netdev=eth0\0" \ 147 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 148 "loadaddr=40010000\0" \ 149 "u-boot=u-boot.bin\0" \ 150 "load=tftp ${loadaddr) ${u-boot}\0" \ 151 "upd=run load; run prog\0" \ 152 "prog=prot off mram" " ;" \ 153 "cp.b ${loadaddr} 0 ${filesize};" \ 154 "save\0" \ 155 "" 156 #endif 157 158 /* Realtime clock */ 159 #undef CONFIG_MCFRTC 160 #define CONFIG_RTC_MCFRRTC 161 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 162 163 /* Timer */ 164 #define CONFIG_MCFTMR 165 #undef CONFIG_MCFPIT 166 167 /* I2c */ 168 #undef CONFIG_SYS_FSL_I2C 169 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 170 /* I2C speed and slave address */ 171 #define CONFIG_SYS_I2C_SPEED 80000 172 #define CONFIG_SYS_I2C_SLAVE 0x7F 173 #define CONFIG_SYS_I2C_OFFSET 0x58000 174 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 175 176 /* DSPI and Serial Flash */ 177 #define CONFIG_CF_SPI 178 #define CONFIG_CF_DSPI 179 #define CONFIG_SERIAL_FLASH 180 #define CONFIG_HARD_SPI 181 #define CONFIG_SYS_SBFHDR_SIZE 0x7 182 #ifdef CONFIG_CMD_SPI 183 184 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 185 DSPI_CTAR_PCSSCK_1CLK | \ 186 DSPI_CTAR_PASC(0) | \ 187 DSPI_CTAR_PDT(0) | \ 188 DSPI_CTAR_CSSCK(0) | \ 189 DSPI_CTAR_ASC(0) | \ 190 DSPI_CTAR_DT(1)) 191 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 192 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 193 #endif 194 195 /* Input, PCI, Flexbus, and VCO */ 196 #define CONFIG_EXTRA_CLOCK 197 198 #define CONFIG_PRAM 2048 /* 2048 KB */ 199 200 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 201 202 #if defined(CONFIG_CMD_KGDB) 203 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 204 #else 205 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 206 #endif 207 /* Print Buffer Size */ 208 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 209 sizeof(CONFIG_SYS_PROMPT) + 16) 210 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 211 /* Boot Argument Buffer Size */ 212 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 213 214 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 215 216 #define CONFIG_SYS_MBAR 0xFC000000 217 218 /* 219 * Low Level Configuration Settings 220 * (address mappings, register initial values, etc.) 221 * You should know what you are doing if you make changes here. 222 */ 223 224 /*----------------------------------------------------------------------- 225 * Definitions for initial stack pointer and data area (in DPRAM) 226 */ 227 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 228 /* End of used area in internal SRAM */ 229 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 230 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 231 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ 232 GENERATED_GBL_DATA_SIZE) - 32) 233 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 234 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 235 236 /*----------------------------------------------------------------------- 237 * Start addresses for the final memory configuration 238 * (Set up by the startup code) 239 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 240 */ 241 #define CONFIG_SYS_SDRAM_BASE 0x40000000 242 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 243 244 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) 245 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 246 #define CONFIG_SYS_DRAM_TEST 247 248 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) 249 #define CONFIG_SERIAL_BOOT 250 #endif 251 252 #if defined(CONFIG_SERIAL_BOOT) 253 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 254 #else 255 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 256 #endif 257 258 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 259 /* Reserve 256 kB for Monitor */ 260 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 261 /* Reserve 256 kB for malloc() */ 262 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 263 264 /* 265 * For booting Linux, the board info and command line data 266 * have to be in the first 8 MB of memory, since this is 267 * the maximum mapped by the Linux kernel during initialization ?? 268 */ 269 /* Initial Memory map for Linux */ 270 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 271 (CONFIG_SYS_SDRAM_SIZE << 20)) 272 273 /* Configuration for environment 274 * Environment is embedded in u-boot in the second sector of the flash 275 */ 276 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ 277 #define CONFIG_ENV_IS_IN_MRAM 1 278 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ 279 #define CONFIG_ENV_SIZE 0x1000 280 #endif 281 282 #if defined(CONFIG_CF_SBF) 283 #define CONFIG_ENV_IS_IN_SPI_FLASH 1 284 #define CONFIG_ENV_SPI_CS 1 285 #define CONFIG_ENV_OFFSET 0x40000 286 #define CONFIG_ENV_SIZE 0x2000 287 #define CONFIG_ENV_SECT_SIZE 0x10000 288 #endif 289 #if defined(CONFIG_SYS_NAND_BOOT) 290 #define CONFIG_ENV_IS_NOWHERE 291 #define CONFIG_ENV_OFFSET 0x80000 292 #define CONFIG_ENV_SIZE 0x20000 293 #define CONFIG_ENV_SECT_SIZE 0x20000 294 #endif 295 #undef CONFIG_ENV_OVERWRITE 296 297 /* FLASH organization */ 298 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 299 300 #undef CONFIG_SYS_FLASH_CFI 301 #ifdef CONFIG_SYS_FLASH_CFI 302 303 #define CONFIG_FLASH_CFI_DRIVER 1 304 /* Max size that the board might have */ 305 #define CONFIG_SYS_FLASH_SIZE 0x1000000 306 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 307 /* max number of memory banks */ 308 #define CONFIG_SYS_MAX_FLASH_BANKS 1 309 /* max number of sectors on one chip */ 310 #define CONFIG_SYS_MAX_FLASH_SECT 270 311 /* "Real" (hardware) sectors protection */ 312 #define CONFIG_SYS_FLASH_PROTECTION 313 #define CONFIG_SYS_FLASH_CHECKSUM 314 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 315 #else 316 /* max number of sectors on one chip */ 317 #define CONFIG_SYS_MAX_FLASH_SECT 270 318 /* max number of sectors on one chip */ 319 #define CONFIG_SYS_MAX_FLASH_BANKS 0 320 #endif 321 322 /* 323 * This is setting for JFFS2 support in u-boot. 324 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 325 */ 326 #ifdef CONFIG_CMD_JFFS2 327 #define CONFIG_JFFS2_DEV "nand0" 328 #define CONFIG_JFFS2_PART_OFFSET (0x800000) 329 #define CONFIG_CMD_MTDPARTS 330 #define CONFIG_MTD_DEVICE 331 #define MTDIDS_DEFAULT "nand0=m54418twr.nand" 332 333 #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \ 334 "7m(kernel)," \ 335 "-(rootfs)" 336 337 #endif 338 339 #ifdef CONFIG_CMD_UBI 340 #define CONFIG_CMD_MTDPARTS 341 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */ 342 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */ 343 #define CONFIG_RBTREE 344 #define MTDIDS_DEFAULT "nand0=NAND" 345 #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \ 346 "-(ubi)" 347 #endif 348 /* Cache Configuration */ 349 #define CONFIG_SYS_CACHELINE_SIZE 16 350 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 351 CONFIG_SYS_INIT_RAM_SIZE - 8) 352 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 353 CONFIG_SYS_INIT_RAM_SIZE - 4) 354 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 355 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 356 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 357 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 358 CF_ACR_EN | CF_ACR_SM_ALL) 359 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 360 CF_CACR_ICINVA | CF_CACR_EUSP) 361 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 362 CF_CACR_DEC | CF_CACR_DDCM_P | \ 363 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 364 365 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 366 CONFIG_SYS_INIT_RAM_SIZE - 12) 367 368 /*----------------------------------------------------------------------- 369 * Memory bank definitions 370 */ 371 /* 372 * CS0 - NOR Flash 16MB 373 * CS1 - Available 374 * CS2 - Available 375 * CS3 - Available 376 * CS4 - Available 377 * CS5 - Available 378 */ 379 380 /* Flash */ 381 #define CONFIG_SYS_CS0_BASE 0x00000000 382 #define CONFIG_SYS_CS0_MASK 0x000F0101 383 #define CONFIG_SYS_CS0_CTRL 0x00001D60 384 385 #endif /* _M54418TWR_H */ 386