1 /* 2 * Configuation settings for the Freescale MCF54418 TWR board. 3 * 4 * Copyright 2010-2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54418TWR_H 15 #define _M54418TWR_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54418TWR /* M54418TWR board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 #define CONFIG_BAUDRATE 115200 26 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 27 28 #undef CONFIG_WATCHDOG 29 30 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 31 32 /* 33 * BOOTP options 34 */ 35 #define CONFIG_BOOTP_BOOTFILESIZE 36 #define CONFIG_BOOTP_BOOTPATH 37 #define CONFIG_BOOTP_GATEWAY 38 #define CONFIG_BOOTP_HOSTNAME 39 40 /* Command line configuration */ 41 #include <config_cmd_default.h> 42 43 #define CONFIG_CMD_BOOTD 44 #define CONFIG_CMD_CACHE 45 #undef CONFIG_CMD_DATE 46 #define CONFIG_CMD_DHCP 47 #define CONFIG_CMD_ELF 48 #undef CONFIG_CMD_FLASH 49 #undef CONFIG_CMD_I2C 50 #undef CONFIG_CMD_JFFS2 51 #undef CONFIG_CMD_UBI 52 #define CONFIG_CMD_MEMORY 53 #define CONFIG_CMD_MISC 54 #define CONFIG_CMD_MII 55 #undef CONFIG_CMD_NAND 56 #define CONFIG_CMD_NFS 57 #define CONFIG_CMD_PING 58 #define CONFIG_CMD_REGINFO 59 #define CONFIG_CMD_SPI 60 #define CONFIG_CMD_SF 61 #undef CONFIG_CMD_IMLS 62 63 #undef CONFIG_CMD_LOADB 64 #undef CONFIG_CMD_LOADS 65 66 /* 67 * NAND FLASH 68 */ 69 #ifdef CONFIG_CMD_NAND 70 #define CONFIG_JFFS2_NAND 71 #define CONFIG_NAND_FSL_NFC 72 #define CONFIG_SYS_NAND_BASE 0xFC0FC000 73 #define CONFIG_SYS_MAX_NAND_DEVICE 1 74 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE 75 #define CONFIG_SYS_NAND_SELECT_DEVICE 76 #endif 77 78 /* Network configuration */ 79 #define CONFIG_MCFFEC 80 #ifdef CONFIG_MCFFEC 81 #define CONFIG_MII 1 82 #define CONFIG_MII_INIT 1 83 #define CONFIG_SYS_DISCOVER_PHY 84 #define CONFIG_SYS_RX_ETH_BUFFER 2 85 #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN 86 #define CONFIG_SYS_TX_ETH_BUFFER 2 87 #define CONFIG_HAS_ETH1 88 89 #define CONFIG_SYS_FEC0_PINMUX 0 90 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 91 #define CONFIG_SYS_FEC1_PINMUX 0 92 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE 93 #define MCFFEC_TOUT_LOOP 50000 94 #define CONFIG_SYS_FEC0_PHYADDR 0 95 #define CONFIG_SYS_FEC1_PHYADDR 1 96 97 #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ 98 99 #ifdef CONFIG_SYS_NAND_BOOT 100 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \ 101 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \ 102 "-(jffs2) console=ttyS0,115200" 103 #else 104 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \ 105 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \ 106 __stringify(CONFIG_IPADDR) " ip=" \ 107 __stringify(CONFIG_IPADDR) ":" \ 108 __stringify(CONFIG_SERVERIP)":" \ 109 __stringify(CONFIG_GATEWAYIP)": " \ 110 __stringify(CONFIG_NETMASK) \ 111 "::eth0:off:rw console=ttyS0,115200" 112 #endif 113 114 #define CONFIG_ETHPRIME "FEC0" 115 #define CONFIG_IPADDR 192.168.1.2 116 #define CONFIG_NETMASK 255.255.255.0 117 #define CONFIG_SERVERIP 192.168.1.1 118 #define CONFIG_GATEWAYIP 192.168.1.1 119 120 #define CONFIG_SYS_FEC_BUF_USE_SRAM 121 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 122 #ifndef CONFIG_SYS_DISCOVER_PHY 123 #define FECDUPLEX FULL 124 #define FECSPEED _100BASET 125 #define LINKSTATUS 1 126 #else 127 #define LINKSTATUS 0 128 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 129 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 130 #endif 131 #endif /* CONFIG_SYS_DISCOVER_PHY */ 132 #endif 133 134 #define CONFIG_HOSTNAME M54418TWR 135 136 #if defined(CONFIG_CF_SBF) 137 /* ST Micro serial flash */ 138 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 139 #define CONFIG_EXTRA_ENV_SETTINGS \ 140 "netdev=eth0\0" \ 141 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 142 "loadaddr=0x40010000\0" \ 143 "sbfhdr=sbfhdr.bin\0" \ 144 "uboot=u-boot.bin\0" \ 145 "load=tftp ${loadaddr} ${sbfhdr};" \ 146 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 147 "upd=run load; run prog\0" \ 148 "prog=sf probe 0:1 1000000 3;" \ 149 "sf erase 0 40000;" \ 150 "sf write ${loadaddr} 0 40000;" \ 151 "save\0" \ 152 "" 153 #elif defined(CONFIG_SYS_NAND_BOOT) 154 #define CONFIG_EXTRA_ENV_SETTINGS \ 155 "netdev=eth0\0" \ 156 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 157 "loadaddr=0x40010000\0" \ 158 "u-boot=u-boot.bin\0" \ 159 "load=tftp ${loadaddr} ${u-boot};\0" \ 160 "upd=run load; run prog\0" \ 161 "prog=nand device 0;" \ 162 "nand erase 0 40000;" \ 163 "nb_update ${loadaddr} ${filesize};" \ 164 "save\0" \ 165 "" 166 #else 167 #define CONFIG_SYS_UBOOT_END 0x3FFFF 168 #define CONFIG_EXTRA_ENV_SETTINGS \ 169 "netdev=eth0\0" \ 170 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 171 "loadaddr=40010000\0" \ 172 "u-boot=u-boot.bin\0" \ 173 "load=tftp ${loadaddr) ${u-boot}\0" \ 174 "upd=run load; run prog\0" \ 175 "prog=prot off mram" " ;" \ 176 "cp.b ${loadaddr} 0 ${filesize};" \ 177 "save\0" \ 178 "" 179 #endif 180 181 /* Realtime clock */ 182 #undef CONFIG_MCFRTC 183 #define CONFIG_RTC_MCFRRTC 184 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 185 186 /* Timer */ 187 #define CONFIG_MCFTMR 188 #undef CONFIG_MCFPIT 189 190 /* I2c */ 191 #undef CONFIG_SYS_FSL_I2C 192 #undef CONFIG_HARD_I2C /* I2C with hardware support */ 193 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 194 /* I2C speed and slave address */ 195 #define CONFIG_SYS_I2C_SPEED 80000 196 #define CONFIG_SYS_I2C_SLAVE 0x7F 197 #define CONFIG_SYS_I2C_OFFSET 0x58000 198 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 199 200 /* DSPI and Serial Flash */ 201 #define CONFIG_CF_SPI 202 #define CONFIG_CF_DSPI 203 #define CONFIG_SERIAL_FLASH 204 #define CONFIG_HARD_SPI 205 #define CONFIG_SYS_SBFHDR_SIZE 0x7 206 #ifdef CONFIG_CMD_SPI 207 # define CONFIG_SPI_FLASH 208 # define CONFIG_SPI_FLASH_ATMEL 209 210 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 211 DSPI_CTAR_PCSSCK_1CLK | \ 212 DSPI_CTAR_PASC(0) | \ 213 DSPI_CTAR_PDT(0) | \ 214 DSPI_CTAR_CSSCK(0) | \ 215 DSPI_CTAR_ASC(0) | \ 216 DSPI_CTAR_DT(1)) 217 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 218 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 219 #endif 220 221 /* Input, PCI, Flexbus, and VCO */ 222 #define CONFIG_EXTRA_CLOCK 223 224 #define CONFIG_PRAM 2048 /* 2048 KB */ 225 226 /* HUSH */ 227 #define CONFIG_SYS_HUSH_PARSER 1 228 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 229 230 #define CONFIG_SYS_PROMPT "-> " 231 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 232 233 #if defined(CONFIG_CMD_KGDB) 234 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 235 #else 236 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 237 #endif 238 /* Print Buffer Size */ 239 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 240 sizeof(CONFIG_SYS_PROMPT) + 16) 241 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 242 /* Boot Argument Buffer Size */ 243 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 244 245 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 246 247 #define CONFIG_SYS_MBAR 0xFC000000 248 249 /* 250 * Low Level Configuration Settings 251 * (address mappings, register initial values, etc.) 252 * You should know what you are doing if you make changes here. 253 */ 254 255 /*----------------------------------------------------------------------- 256 * Definitions for initial stack pointer and data area (in DPRAM) 257 */ 258 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 259 /* End of used area in internal SRAM */ 260 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 261 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 262 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ 263 GENERATED_GBL_DATA_SIZE) - 32) 264 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 265 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 266 267 /*----------------------------------------------------------------------- 268 * Start addresses for the final memory configuration 269 * (Set up by the startup code) 270 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 271 */ 272 #define CONFIG_SYS_SDRAM_BASE 0x40000000 273 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 274 275 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) 276 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 277 #define CONFIG_SYS_DRAM_TEST 278 279 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) 280 #define CONFIG_SERIAL_BOOT 281 #endif 282 283 #if defined(CONFIG_SERIAL_BOOT) 284 #define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400) 285 #else 286 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 287 #endif 288 289 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 290 /* Reserve 256 kB for Monitor */ 291 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 292 /* Reserve 256 kB for malloc() */ 293 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 294 295 /* 296 * For booting Linux, the board info and command line data 297 * have to be in the first 8 MB of memory, since this is 298 * the maximum mapped by the Linux kernel during initialization ?? 299 */ 300 /* Initial Memory map for Linux */ 301 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 302 (CONFIG_SYS_SDRAM_SIZE << 20)) 303 304 /* Configuration for environment 305 * Environment is embedded in u-boot in the second sector of the flash 306 */ 307 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ 308 #define CONFIG_SYS_NO_FLASH 309 #define CONFIG_ENV_IS_IN_MRAM 1 310 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ 311 #define CONFIG_ENV_SIZE 0x1000 312 #endif 313 314 #if defined(CONFIG_CF_SBF) 315 #define CONFIG_SYS_NO_FLASH 316 #define CONFIG_ENV_IS_IN_SPI_FLASH 1 317 #define CONFIG_ENV_SPI_CS 1 318 #define CONFIG_ENV_OFFSET 0x40000 319 #define CONFIG_ENV_SIZE 0x2000 320 #define CONFIG_ENV_SECT_SIZE 0x10000 321 #endif 322 #if defined(CONFIG_SYS_NAND_BOOT) 323 #define CONFIG_SYS_NO_FLASH 324 #define CONFIG_ENV_IS_NOWHERE 325 #define CONFIG_ENV_OFFSET 0x80000 326 #define CONFIG_ENV_SIZE 0x20000 327 #define CONFIG_ENV_SECT_SIZE 0x20000 328 #endif 329 #undef CONFIG_ENV_OVERWRITE 330 331 /* FLASH organization */ 332 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 333 334 #undef CONFIG_SYS_FLASH_CFI 335 #ifdef CONFIG_SYS_FLASH_CFI 336 337 #define CONFIG_FLASH_CFI_DRIVER 1 338 /* Max size that the board might have */ 339 #define CONFIG_SYS_FLASH_SIZE 0x1000000 340 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 341 /* max number of memory banks */ 342 #define CONFIG_SYS_MAX_FLASH_BANKS 1 343 /* max number of sectors on one chip */ 344 #define CONFIG_SYS_MAX_FLASH_SECT 270 345 /* "Real" (hardware) sectors protection */ 346 #define CONFIG_SYS_FLASH_PROTECTION 347 #define CONFIG_SYS_FLASH_CHECKSUM 348 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 349 #else 350 /* max number of sectors on one chip */ 351 #define CONFIG_SYS_MAX_FLASH_SECT 270 352 /* max number of sectors on one chip */ 353 #define CONFIG_SYS_MAX_FLASH_BANKS 0 354 #endif 355 356 /* 357 * This is setting for JFFS2 support in u-boot. 358 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 359 */ 360 #ifdef CONFIG_CMD_JFFS2 361 #define CONFIG_JFFS2_DEV "nand0" 362 #define CONFIG_JFFS2_PART_OFFSET (0x800000) 363 #define CONFIG_CMD_MTDPARTS 364 #define CONFIG_MTD_DEVICE 365 #define MTDIDS_DEFAULT "nand0=m54418twr.nand" 366 367 #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \ 368 "7m(kernel)," \ 369 "-(rootfs)" 370 371 #endif 372 373 #ifdef CONFIG_CMD_UBI 374 #define CONFIG_CMD_MTDPARTS 375 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */ 376 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */ 377 #define CONFIG_RBTREE 378 #define MTDIDS_DEFAULT "nand0=NAND" 379 #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \ 380 "-(ubi)" 381 #endif 382 /* Cache Configuration */ 383 #define CONFIG_SYS_CACHELINE_SIZE 16 384 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 385 CONFIG_SYS_INIT_RAM_SIZE - 8) 386 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 387 CONFIG_SYS_INIT_RAM_SIZE - 4) 388 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 389 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 390 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 391 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 392 CF_ACR_EN | CF_ACR_SM_ALL) 393 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 394 CF_CACR_ICINVA | CF_CACR_EUSP) 395 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 396 CF_CACR_DEC | CF_CACR_DDCM_P | \ 397 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 398 399 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 400 CONFIG_SYS_INIT_RAM_SIZE - 12) 401 402 /*----------------------------------------------------------------------- 403 * Memory bank definitions 404 */ 405 /* 406 * CS0 - NOR Flash 16MB 407 * CS1 - Available 408 * CS2 - Available 409 * CS3 - Available 410 * CS4 - Available 411 * CS5 - Available 412 */ 413 414 /* Flash */ 415 #define CONFIG_SYS_CS0_BASE 0x00000000 416 #define CONFIG_SYS_CS0_MASK 0x000F0101 417 #define CONFIG_SYS_CS0_CTRL 0x00001D60 418 419 #endif /* _M54418TWR_H */ 420