1 /* 2 * Configuation settings for the Freescale MCF54418 TWR board. 3 * 4 * Copyright 2010-2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54418TWR_H 15 #define _M54418TWR_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54418TWR /* M54418TWR board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 #define CONFIG_BAUDRATE 115200 26 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 27 28 #undef CONFIG_WATCHDOG 29 30 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 31 32 /* 33 * BOOTP options 34 */ 35 #define CONFIG_BOOTP_BOOTFILESIZE 36 #define CONFIG_BOOTP_BOOTPATH 37 #define CONFIG_BOOTP_GATEWAY 38 #define CONFIG_BOOTP_HOSTNAME 39 40 /* Command line configuration */ 41 #include <config_cmd_default.h> 42 43 #define CONFIG_CMD_BOOTD 44 #define CONFIG_CMD_CACHE 45 #undef CONFIG_CMD_DATE 46 #define CONFIG_CMD_DHCP 47 #define CONFIG_CMD_ELF 48 #undef CONFIG_CMD_FLASH 49 #undef CONFIG_CMD_I2C 50 #undef CONFIG_CMD_JFFS2 51 #undef CONFIG_CMD_UBI 52 #define CONFIG_CMD_MEMORY 53 #define CONFIG_CMD_MISC 54 #define CONFIG_CMD_MII 55 #undef CONFIG_CMD_NAND 56 #define CONFIG_CMD_NET 57 #define CONFIG_CMD_NFS 58 #define CONFIG_CMD_PING 59 #define CONFIG_CMD_REGINFO 60 #define CONFIG_CMD_SPI 61 #define CONFIG_CMD_SF 62 #undef CONFIG_CMD_IMLS 63 64 #undef CONFIG_CMD_LOADB 65 #undef CONFIG_CMD_LOADS 66 67 /* 68 * NAND FLASH 69 */ 70 #ifdef CONFIG_CMD_NAND 71 #define CONFIG_JFFS2_NAND 72 #define CONFIG_NAND_FSL_NFC 73 #define CONFIG_SYS_NAND_BASE 0xFC0FC000 74 #define CONFIG_SYS_MAX_NAND_DEVICE 1 75 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE 76 #define CONFIG_SYS_NAND_SELECT_DEVICE 77 #endif 78 79 /* Network configuration */ 80 #define CONFIG_MCFFEC 81 #ifdef CONFIG_MCFFEC 82 #define CONFIG_NET_MULTI 1 83 #define CONFIG_MII 1 84 #define CONFIG_MII_INIT 1 85 #define CONFIG_SYS_DISCOVER_PHY 86 #define CONFIG_SYS_RX_ETH_BUFFER 2 87 #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN 88 #define CONFIG_SYS_TX_ETH_BUFFER 2 89 #define CONFIG_HAS_ETH1 90 91 #define CONFIG_SYS_FEC0_PINMUX 0 92 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 93 #define CONFIG_SYS_FEC1_PINMUX 0 94 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE 95 #define MCFFEC_TOUT_LOOP 50000 96 #define CONFIG_SYS_FEC0_PHYADDR 0 97 #define CONFIG_SYS_FEC1_PHYADDR 1 98 99 #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ 100 101 #ifdef CONFIG_SYS_NAND_BOOT 102 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \ 103 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \ 104 "-(jffs2) console=ttyS0,115200" 105 #else 106 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \ 107 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \ 108 __stringify(CONFIG_IPADDR) " ip=" \ 109 __stringify(CONFIG_IPADDR) ":" \ 110 __stringify(CONFIG_SERVERIP)":" \ 111 __stringify(CONFIG_GATEWAYIP)": " \ 112 __stringify(CONFIG_NETMASK) \ 113 "::eth0:off:rw console=ttyS0,115200" 114 #endif 115 116 #define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 117 #define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 118 #define CONFIG_ETHPRIME "FEC0" 119 #define CONFIG_IPADDR 192.168.1.2 120 #define CONFIG_NETMASK 255.255.255.0 121 #define CONFIG_SERVERIP 192.168.1.1 122 #define CONFIG_GATEWAYIP 192.168.1.1 123 124 #define CONFIG_OVERWRITE_ETHADDR_ONCE 125 #define CONFIG_SYS_FEC_BUF_USE_SRAM 126 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 127 #ifndef CONFIG_SYS_DISCOVER_PHY 128 #define FECDUPLEX FULL 129 #define FECSPEED _100BASET 130 #define LINKSTATUS 1 131 #else 132 #define LINKSTATUS 0 133 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 134 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 135 #endif 136 #endif /* CONFIG_SYS_DISCOVER_PHY */ 137 #endif 138 139 #define CONFIG_HOSTNAME M54418TWR 140 141 #if defined(CONFIG_CF_SBF) 142 /* ST Micro serial flash */ 143 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 144 #define CONFIG_EXTRA_ENV_SETTINGS \ 145 "netdev=eth0\0" \ 146 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 147 "loadaddr=0x40010000\0" \ 148 "sbfhdr=sbfhdr.bin\0" \ 149 "uboot=u-boot.bin\0" \ 150 "load=tftp ${loadaddr} ${sbfhdr};" \ 151 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 152 "upd=run load; run prog\0" \ 153 "prog=sf probe 0:1 1000000 3;" \ 154 "sf erase 0 40000;" \ 155 "sf write ${loadaddr} 0 40000;" \ 156 "save\0" \ 157 "" 158 #elif defined(CONFIG_SYS_NAND_BOOT) 159 #define CONFIG_EXTRA_ENV_SETTINGS \ 160 "netdev=eth0\0" \ 161 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 162 "loadaddr=0x40010000\0" \ 163 "u-boot=u-boot.bin\0" \ 164 "load=tftp ${loadaddr} ${u-boot};\0" \ 165 "upd=run load; run prog\0" \ 166 "prog=nand device 0;" \ 167 "nand erase 0 40000;" \ 168 "nb_update ${loadaddr} ${filesize};" \ 169 "save\0" \ 170 "" 171 #else 172 #define CONFIG_SYS_UBOOT_END 0x3FFFF 173 #define CONFIG_EXTRA_ENV_SETTINGS \ 174 "netdev=eth0\0" \ 175 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 176 "loadaddr=40010000\0" \ 177 "u-boot=u-boot.bin\0" \ 178 "load=tftp ${loadaddr) ${u-boot}\0" \ 179 "upd=run load; run prog\0" \ 180 "prog=prot off mram" " ;" \ 181 "cp.b ${loadaddr} 0 ${filesize};" \ 182 "save\0" \ 183 "" 184 #endif 185 186 /* Realtime clock */ 187 #undef CONFIG_MCFRTC 188 #define CONFIG_RTC_MCFRRTC 189 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 190 191 /* Timer */ 192 #define CONFIG_MCFTMR 193 #undef CONFIG_MCFPIT 194 195 /* I2c */ 196 #undef CONFIG_SYS_FSL_I2C 197 #undef CONFIG_HARD_I2C /* I2C with hardware support */ 198 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 199 /* I2C speed and slave address */ 200 #define CONFIG_SYS_I2C_SPEED 80000 201 #define CONFIG_SYS_I2C_SLAVE 0x7F 202 #define CONFIG_SYS_I2C_OFFSET 0x58000 203 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 204 205 /* DSPI and Serial Flash */ 206 #define CONFIG_CF_SPI 207 #define CONFIG_CF_DSPI 208 #define CONFIG_SERIAL_FLASH 209 #define CONFIG_HARD_SPI 210 #define CONFIG_SYS_SBFHDR_SIZE 0x7 211 #ifdef CONFIG_CMD_SPI 212 # define CONFIG_SPI_FLASH 213 # define CONFIG_SPI_FLASH_ATMEL 214 215 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 216 DSPI_CTAR_PCSSCK_1CLK | \ 217 DSPI_CTAR_PASC(0) | \ 218 DSPI_CTAR_PDT(0) | \ 219 DSPI_CTAR_CSSCK(0) | \ 220 DSPI_CTAR_ASC(0) | \ 221 DSPI_CTAR_DT(1)) 222 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 223 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 224 #endif 225 226 /* Input, PCI, Flexbus, and VCO */ 227 #define CONFIG_EXTRA_CLOCK 228 229 #define CONFIG_PRAM 2048 /* 2048 KB */ 230 231 /* HUSH */ 232 #define CONFIG_SYS_HUSH_PARSER 1 233 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 234 235 #define CONFIG_SYS_PROMPT "-> " 236 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 237 238 #if defined(CONFIG_CMD_KGDB) 239 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 240 #else 241 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 242 #endif 243 /* Print Buffer Size */ 244 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 245 sizeof(CONFIG_SYS_PROMPT) + 16) 246 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 247 /* Boot Argument Buffer Size */ 248 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 249 250 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 251 252 #define CONFIG_SYS_MBAR 0xFC000000 253 254 /* 255 * Low Level Configuration Settings 256 * (address mappings, register initial values, etc.) 257 * You should know what you are doing if you make changes here. 258 */ 259 260 /*----------------------------------------------------------------------- 261 * Definitions for initial stack pointer and data area (in DPRAM) 262 */ 263 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 264 /* End of used area in internal SRAM */ 265 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 266 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 267 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ 268 GENERATED_GBL_DATA_SIZE) - 32) 269 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 270 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 271 272 /*----------------------------------------------------------------------- 273 * Start addresses for the final memory configuration 274 * (Set up by the startup code) 275 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 276 */ 277 #define CONFIG_SYS_SDRAM_BASE 0x40000000 278 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 279 280 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) 281 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 282 #define CONFIG_SYS_DRAM_TEST 283 284 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) 285 #define CONFIG_SERIAL_BOOT 286 #endif 287 288 #if defined(CONFIG_SERIAL_BOOT) 289 #define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400) 290 #else 291 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 292 #endif 293 294 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 295 /* Reserve 256 kB for Monitor */ 296 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 297 /* Reserve 256 kB for malloc() */ 298 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 299 300 /* 301 * For booting Linux, the board info and command line data 302 * have to be in the first 8 MB of memory, since this is 303 * the maximum mapped by the Linux kernel during initialization ?? 304 */ 305 /* Initial Memory map for Linux */ 306 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 307 (CONFIG_SYS_SDRAM_SIZE << 20)) 308 309 /* Configuration for environment 310 * Environment is embedded in u-boot in the second sector of the flash 311 */ 312 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ 313 #define CONFIG_SYS_NO_FLASH 314 #define CONFIG_ENV_IS_IN_MRAM 1 315 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ 316 #define CONFIG_ENV_SIZE 0x1000 317 #endif 318 319 #if defined(CONFIG_CF_SBF) 320 #define CONFIG_SYS_NO_FLASH 321 #define CONFIG_ENV_IS_IN_SPI_FLASH 1 322 #define CONFIG_ENV_SPI_CS 1 323 #define CONFIG_ENV_OFFSET 0x40000 324 #define CONFIG_ENV_SIZE 0x2000 325 #define CONFIG_ENV_SECT_SIZE 0x10000 326 #endif 327 #if defined(CONFIG_SYS_NAND_BOOT) 328 #define CONFIG_SYS_NO_FLASH 329 #define CONFIG_ENV_IS_NOWHERE 330 #define CONFIG_ENV_OFFSET 0x80000 331 #define CONFIG_ENV_SIZE 0x20000 332 #define CONFIG_ENV_SECT_SIZE 0x20000 333 #endif 334 #undef CONFIG_ENV_OVERWRITE 335 336 /* FLASH organization */ 337 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 338 339 #undef CONFIG_SYS_FLASH_CFI 340 #ifdef CONFIG_SYS_FLASH_CFI 341 342 #define CONFIG_FLASH_CFI_DRIVER 1 343 /* Max size that the board might have */ 344 #define CONFIG_SYS_FLASH_SIZE 0x1000000 345 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 346 /* max number of memory banks */ 347 #define CONFIG_SYS_MAX_FLASH_BANKS 1 348 /* max number of sectors on one chip */ 349 #define CONFIG_SYS_MAX_FLASH_SECT 270 350 /* "Real" (hardware) sectors protection */ 351 #define CONFIG_SYS_FLASH_PROTECTION 352 #define CONFIG_SYS_FLASH_CHECKSUM 353 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 354 #else 355 /* max number of sectors on one chip */ 356 #define CONFIG_SYS_MAX_FLASH_SECT 270 357 /* max number of sectors on one chip */ 358 #define CONFIG_SYS_MAX_FLASH_BANKS 0 359 #endif 360 361 /* 362 * This is setting for JFFS2 support in u-boot. 363 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 364 */ 365 #ifdef CONFIG_CMD_JFFS2 366 #define CONFIG_JFFS2_DEV "nand0" 367 #define CONFIG_JFFS2_PART_OFFSET (0x800000) 368 #define CONFIG_CMD_MTDPARTS 369 #define CONFIG_MTD_DEVICE 370 #define MTDIDS_DEFAULT "nand0=m54418twr.nand" 371 372 #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \ 373 "7m(kernel)," \ 374 "-(rootfs)" 375 376 #endif 377 378 #ifdef CONFIG_CMD_UBI 379 #define CONFIG_CMD_MTDPARTS 380 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */ 381 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */ 382 #define CONFIG_RBTREE 383 #define MTDIDS_DEFAULT "nand0=NAND" 384 #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \ 385 "-(ubi)" 386 #endif 387 /* Cache Configuration */ 388 #define CONFIG_SYS_CACHELINE_SIZE 16 389 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 390 CONFIG_SYS_INIT_RAM_SIZE - 8) 391 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 392 CONFIG_SYS_INIT_RAM_SIZE - 4) 393 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 394 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 395 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 396 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 397 CF_ACR_EN | CF_ACR_SM_ALL) 398 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 399 CF_CACR_ICINVA | CF_CACR_EUSP) 400 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 401 CF_CACR_DEC | CF_CACR_DDCM_P | \ 402 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 403 404 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 405 CONFIG_SYS_INIT_RAM_SIZE - 12) 406 407 /*----------------------------------------------------------------------- 408 * Memory bank definitions 409 */ 410 /* 411 * CS0 - NOR Flash 16MB 412 * CS1 - Available 413 * CS2 - Available 414 * CS3 - Available 415 * CS4 - Available 416 * CS5 - Available 417 */ 418 419 /* Flash */ 420 #define CONFIG_SYS_CS0_BASE 0x00000000 421 #define CONFIG_SYS_CS0_MASK 0x000F0101 422 #define CONFIG_SYS_CS0_CTRL 0x00001D60 423 424 #endif /* _M54418TWR_H */ 425