1 /* 2 * Configuation settings for the Freescale MCF54418 TWR board. 3 * 4 * Copyright 2010-2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M54418TWR_H 15 #define _M54418TWR_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M54418TWR /* M54418TWR board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 #define CONFIG_BAUDRATE 115200 26 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 27 28 #undef CONFIG_WATCHDOG 29 30 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 31 32 /* 33 * BOOTP options 34 */ 35 #define CONFIG_BOOTP_BOOTFILESIZE 36 #define CONFIG_BOOTP_BOOTPATH 37 #define CONFIG_BOOTP_GATEWAY 38 #define CONFIG_BOOTP_HOSTNAME 39 40 /* Command line configuration */ 41 #include <config_cmd_default.h> 42 43 #define CONFIG_CMD_BOOTD 44 #define CONFIG_CMD_CACHE 45 #undef CONFIG_CMD_DATE 46 #define CONFIG_CMD_DHCP 47 #define CONFIG_CMD_ELF 48 #undef CONFIG_CMD_FLASH 49 #undef CONFIG_CMD_I2C 50 #undef CONFIG_CMD_JFFS2 51 #undef CONFIG_CMD_UBI 52 #define CONFIG_CMD_MEMORY 53 #define CONFIG_CMD_MISC 54 #define CONFIG_CMD_MII 55 #undef CONFIG_CMD_NAND 56 #define CONFIG_CMD_NET 57 #define CONFIG_CMD_NFS 58 #define CONFIG_CMD_PING 59 #define CONFIG_CMD_REGINFO 60 #define CONFIG_CMD_SPI 61 #define CONFIG_CMD_SF 62 #undef CONFIG_CMD_IMLS 63 64 #undef CONFIG_CMD_LOADB 65 #undef CONFIG_CMD_LOADS 66 67 /* 68 * NAND FLASH 69 */ 70 #ifdef CONFIG_CMD_NAND 71 #define CONFIG_JFFS2_NAND 72 #define CONFIG_NAND_FSL_NFC 73 #define CONFIG_SYS_NAND_BASE 0xFC0FC000 74 #define CONFIG_SYS_MAX_NAND_DEVICE 1 75 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE 76 #define CONFIG_SYS_NAND_SELECT_DEVICE 77 #endif 78 79 /* Network configuration */ 80 #define CONFIG_MCFFEC 81 #ifdef CONFIG_MCFFEC 82 #define CONFIG_NET_MULTI 1 83 #define CONFIG_MII 1 84 #define CONFIG_MII_INIT 1 85 #define CONFIG_SYS_DISCOVER_PHY 86 #define CONFIG_SYS_RX_ETH_BUFFER 2 87 #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN 88 #define CONFIG_SYS_TX_ETH_BUFFER 2 89 #define CONFIG_HAS_ETH1 90 91 #define CONFIG_SYS_FEC0_PINMUX 0 92 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 93 #define CONFIG_SYS_FEC1_PINMUX 0 94 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE 95 #define MCFFEC_TOUT_LOOP 50000 96 #define CONFIG_SYS_FEC0_PHYADDR 0 97 #define CONFIG_SYS_FEC1_PHYADDR 1 98 99 #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ 100 101 #ifdef CONFIG_SYS_NAND_BOOT 102 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \ 103 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \ 104 "-(jffs2) console=ttyS0,115200" 105 #else 106 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \ 107 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \ 108 __stringify(CONFIG_IPADDR) " ip=" \ 109 __stringify(CONFIG_IPADDR) ":" \ 110 __stringify(CONFIG_SERVERIP)":" \ 111 __stringify(CONFIG_GATEWAYIP)": " \ 112 __stringify(CONFIG_NETMASK) \ 113 "::eth0:off:rw console=ttyS0,115200" 114 #endif 115 116 #define CONFIG_ETHPRIME "FEC0" 117 #define CONFIG_IPADDR 192.168.1.2 118 #define CONFIG_NETMASK 255.255.255.0 119 #define CONFIG_SERVERIP 192.168.1.1 120 #define CONFIG_GATEWAYIP 192.168.1.1 121 122 #define CONFIG_SYS_FEC_BUF_USE_SRAM 123 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 124 #ifndef CONFIG_SYS_DISCOVER_PHY 125 #define FECDUPLEX FULL 126 #define FECSPEED _100BASET 127 #define LINKSTATUS 1 128 #else 129 #define LINKSTATUS 0 130 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 131 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 132 #endif 133 #endif /* CONFIG_SYS_DISCOVER_PHY */ 134 #endif 135 136 #define CONFIG_HOSTNAME M54418TWR 137 138 #if defined(CONFIG_CF_SBF) 139 /* ST Micro serial flash */ 140 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 141 #define CONFIG_EXTRA_ENV_SETTINGS \ 142 "netdev=eth0\0" \ 143 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 144 "loadaddr=0x40010000\0" \ 145 "sbfhdr=sbfhdr.bin\0" \ 146 "uboot=u-boot.bin\0" \ 147 "load=tftp ${loadaddr} ${sbfhdr};" \ 148 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 149 "upd=run load; run prog\0" \ 150 "prog=sf probe 0:1 1000000 3;" \ 151 "sf erase 0 40000;" \ 152 "sf write ${loadaddr} 0 40000;" \ 153 "save\0" \ 154 "" 155 #elif defined(CONFIG_SYS_NAND_BOOT) 156 #define CONFIG_EXTRA_ENV_SETTINGS \ 157 "netdev=eth0\0" \ 158 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 159 "loadaddr=0x40010000\0" \ 160 "u-boot=u-boot.bin\0" \ 161 "load=tftp ${loadaddr} ${u-boot};\0" \ 162 "upd=run load; run prog\0" \ 163 "prog=nand device 0;" \ 164 "nand erase 0 40000;" \ 165 "nb_update ${loadaddr} ${filesize};" \ 166 "save\0" \ 167 "" 168 #else 169 #define CONFIG_SYS_UBOOT_END 0x3FFFF 170 #define CONFIG_EXTRA_ENV_SETTINGS \ 171 "netdev=eth0\0" \ 172 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 173 "loadaddr=40010000\0" \ 174 "u-boot=u-boot.bin\0" \ 175 "load=tftp ${loadaddr) ${u-boot}\0" \ 176 "upd=run load; run prog\0" \ 177 "prog=prot off mram" " ;" \ 178 "cp.b ${loadaddr} 0 ${filesize};" \ 179 "save\0" \ 180 "" 181 #endif 182 183 /* Realtime clock */ 184 #undef CONFIG_MCFRTC 185 #define CONFIG_RTC_MCFRRTC 186 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 187 188 /* Timer */ 189 #define CONFIG_MCFTMR 190 #undef CONFIG_MCFPIT 191 192 /* I2c */ 193 #undef CONFIG_SYS_FSL_I2C 194 #undef CONFIG_HARD_I2C /* I2C with hardware support */ 195 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 196 /* I2C speed and slave address */ 197 #define CONFIG_SYS_I2C_SPEED 80000 198 #define CONFIG_SYS_I2C_SLAVE 0x7F 199 #define CONFIG_SYS_I2C_OFFSET 0x58000 200 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 201 202 /* DSPI and Serial Flash */ 203 #define CONFIG_CF_SPI 204 #define CONFIG_CF_DSPI 205 #define CONFIG_SERIAL_FLASH 206 #define CONFIG_HARD_SPI 207 #define CONFIG_SYS_SBFHDR_SIZE 0x7 208 #ifdef CONFIG_CMD_SPI 209 # define CONFIG_SPI_FLASH 210 # define CONFIG_SPI_FLASH_ATMEL 211 212 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 213 DSPI_CTAR_PCSSCK_1CLK | \ 214 DSPI_CTAR_PASC(0) | \ 215 DSPI_CTAR_PDT(0) | \ 216 DSPI_CTAR_CSSCK(0) | \ 217 DSPI_CTAR_ASC(0) | \ 218 DSPI_CTAR_DT(1)) 219 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 220 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 221 #endif 222 223 /* Input, PCI, Flexbus, and VCO */ 224 #define CONFIG_EXTRA_CLOCK 225 226 #define CONFIG_PRAM 2048 /* 2048 KB */ 227 228 /* HUSH */ 229 #define CONFIG_SYS_HUSH_PARSER 1 230 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 231 232 #define CONFIG_SYS_PROMPT "-> " 233 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 234 235 #if defined(CONFIG_CMD_KGDB) 236 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 237 #else 238 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 239 #endif 240 /* Print Buffer Size */ 241 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 242 sizeof(CONFIG_SYS_PROMPT) + 16) 243 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 244 /* Boot Argument Buffer Size */ 245 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 246 247 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 248 249 #define CONFIG_SYS_MBAR 0xFC000000 250 251 /* 252 * Low Level Configuration Settings 253 * (address mappings, register initial values, etc.) 254 * You should know what you are doing if you make changes here. 255 */ 256 257 /*----------------------------------------------------------------------- 258 * Definitions for initial stack pointer and data area (in DPRAM) 259 */ 260 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 261 /* End of used area in internal SRAM */ 262 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 263 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 264 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ 265 GENERATED_GBL_DATA_SIZE) - 32) 266 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 267 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 268 269 /*----------------------------------------------------------------------- 270 * Start addresses for the final memory configuration 271 * (Set up by the startup code) 272 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 273 */ 274 #define CONFIG_SYS_SDRAM_BASE 0x40000000 275 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 276 277 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) 278 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 279 #define CONFIG_SYS_DRAM_TEST 280 281 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) 282 #define CONFIG_SERIAL_BOOT 283 #endif 284 285 #if defined(CONFIG_SERIAL_BOOT) 286 #define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400) 287 #else 288 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 289 #endif 290 291 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 292 /* Reserve 256 kB for Monitor */ 293 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 294 /* Reserve 256 kB for malloc() */ 295 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 296 297 /* 298 * For booting Linux, the board info and command line data 299 * have to be in the first 8 MB of memory, since this is 300 * the maximum mapped by the Linux kernel during initialization ?? 301 */ 302 /* Initial Memory map for Linux */ 303 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 304 (CONFIG_SYS_SDRAM_SIZE << 20)) 305 306 /* Configuration for environment 307 * Environment is embedded in u-boot in the second sector of the flash 308 */ 309 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ 310 #define CONFIG_SYS_NO_FLASH 311 #define CONFIG_ENV_IS_IN_MRAM 1 312 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ 313 #define CONFIG_ENV_SIZE 0x1000 314 #endif 315 316 #if defined(CONFIG_CF_SBF) 317 #define CONFIG_SYS_NO_FLASH 318 #define CONFIG_ENV_IS_IN_SPI_FLASH 1 319 #define CONFIG_ENV_SPI_CS 1 320 #define CONFIG_ENV_OFFSET 0x40000 321 #define CONFIG_ENV_SIZE 0x2000 322 #define CONFIG_ENV_SECT_SIZE 0x10000 323 #endif 324 #if defined(CONFIG_SYS_NAND_BOOT) 325 #define CONFIG_SYS_NO_FLASH 326 #define CONFIG_ENV_IS_NOWHERE 327 #define CONFIG_ENV_OFFSET 0x80000 328 #define CONFIG_ENV_SIZE 0x20000 329 #define CONFIG_ENV_SECT_SIZE 0x20000 330 #endif 331 #undef CONFIG_ENV_OVERWRITE 332 333 /* FLASH organization */ 334 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 335 336 #undef CONFIG_SYS_FLASH_CFI 337 #ifdef CONFIG_SYS_FLASH_CFI 338 339 #define CONFIG_FLASH_CFI_DRIVER 1 340 /* Max size that the board might have */ 341 #define CONFIG_SYS_FLASH_SIZE 0x1000000 342 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 343 /* max number of memory banks */ 344 #define CONFIG_SYS_MAX_FLASH_BANKS 1 345 /* max number of sectors on one chip */ 346 #define CONFIG_SYS_MAX_FLASH_SECT 270 347 /* "Real" (hardware) sectors protection */ 348 #define CONFIG_SYS_FLASH_PROTECTION 349 #define CONFIG_SYS_FLASH_CHECKSUM 350 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 351 #else 352 /* max number of sectors on one chip */ 353 #define CONFIG_SYS_MAX_FLASH_SECT 270 354 /* max number of sectors on one chip */ 355 #define CONFIG_SYS_MAX_FLASH_BANKS 0 356 #endif 357 358 /* 359 * This is setting for JFFS2 support in u-boot. 360 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 361 */ 362 #ifdef CONFIG_CMD_JFFS2 363 #define CONFIG_JFFS2_DEV "nand0" 364 #define CONFIG_JFFS2_PART_OFFSET (0x800000) 365 #define CONFIG_CMD_MTDPARTS 366 #define CONFIG_MTD_DEVICE 367 #define MTDIDS_DEFAULT "nand0=m54418twr.nand" 368 369 #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \ 370 "7m(kernel)," \ 371 "-(rootfs)" 372 373 #endif 374 375 #ifdef CONFIG_CMD_UBI 376 #define CONFIG_CMD_MTDPARTS 377 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */ 378 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */ 379 #define CONFIG_RBTREE 380 #define MTDIDS_DEFAULT "nand0=NAND" 381 #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \ 382 "-(ubi)" 383 #endif 384 /* Cache Configuration */ 385 #define CONFIG_SYS_CACHELINE_SIZE 16 386 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 387 CONFIG_SYS_INIT_RAM_SIZE - 8) 388 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 389 CONFIG_SYS_INIT_RAM_SIZE - 4) 390 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 391 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 392 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 393 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 394 CF_ACR_EN | CF_ACR_SM_ALL) 395 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 396 CF_CACR_ICINVA | CF_CACR_EUSP) 397 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 398 CF_CACR_DEC | CF_CACR_DDCM_P | \ 399 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 400 401 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 402 CONFIG_SYS_INIT_RAM_SIZE - 12) 403 404 /*----------------------------------------------------------------------- 405 * Memory bank definitions 406 */ 407 /* 408 * CS0 - NOR Flash 16MB 409 * CS1 - Available 410 * CS2 - Available 411 * CS3 - Available 412 * CS4 - Available 413 * CS5 - Available 414 */ 415 416 /* Flash */ 417 #define CONFIG_SYS_CS0_BASE 0x00000000 418 #define CONFIG_SYS_CS0_MASK 0x000F0101 419 #define CONFIG_SYS_CS0_CTRL 0x00001D60 420 421 #endif /* _M54418TWR_H */ 422