1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Freescale MCF5373 FireEngine board. 4 * 5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M5373EVB_H 14 #define _M5373EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21 #define CONFIG_MCFUART 22 #define CONFIG_SYS_UART_PORT (0) 23 24 #undef CONFIG_WATCHDOG 25 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ 26 27 #define CONFIG_SYS_UNIFY_CACHE 28 29 #define CONFIG_MCFFEC 30 #ifdef CONFIG_MCFFEC 31 # define CONFIG_MII 1 32 # define CONFIG_MII_INIT 1 33 # define CONFIG_SYS_DISCOVER_PHY 34 # define CONFIG_SYS_RX_ETH_BUFFER 8 35 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 36 37 # define CONFIG_SYS_FEC0_PINMUX 0 38 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 39 # define MCFFEC_TOUT_LOOP 50000 40 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 41 # ifndef CONFIG_SYS_DISCOVER_PHY 42 # define FECDUPLEX FULL 43 # define FECSPEED _100BASET 44 # else 45 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 46 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 47 # endif 48 # endif /* CONFIG_SYS_DISCOVER_PHY */ 49 #endif 50 51 #define CONFIG_MCFRTC 52 #undef RTC_DEBUG 53 54 /* Timer */ 55 #define CONFIG_MCFTMR 56 #undef CONFIG_MCFPIT 57 58 /* I2C */ 59 #define CONFIG_SYS_I2C 60 #define CONFIG_SYS_I2C_FSL 61 #define CONFIG_SYS_FSL_I2C_SPEED 80000 62 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 63 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 64 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 65 66 #define CONFIG_UDP_CHECKSUM 67 68 #ifdef CONFIG_MCFFEC 69 # define CONFIG_IPADDR 192.162.1.2 70 # define CONFIG_NETMASK 255.255.255.0 71 # define CONFIG_SERVERIP 192.162.1.1 72 # define CONFIG_GATEWAYIP 192.162.1.1 73 #endif /* FEC_ENET */ 74 75 #define CONFIG_HOSTNAME "M5373EVB" 76 #define CONFIG_EXTRA_ENV_SETTINGS \ 77 "netdev=eth0\0" \ 78 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 79 "u-boot=u-boot.bin\0" \ 80 "load=tftp ${loadaddr) ${u-boot}\0" \ 81 "upd=run load; run prog\0" \ 82 "prog=prot off 0 3ffff;" \ 83 "era 0 3ffff;" \ 84 "cp.b ${loadaddr} 0 ${filesize};" \ 85 "save\0" \ 86 "" 87 88 #define CONFIG_PRAM 512 /* 512 KB */ 89 90 #define CONFIG_SYS_LOAD_ADDR 0x40010000 91 92 #define CONFIG_SYS_CLK 80000000 93 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 94 95 #define CONFIG_SYS_MBAR 0xFC000000 96 97 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 98 99 /* 100 * Low Level Configuration Settings 101 * (address mappings, register initial values, etc.) 102 * You should know what you are doing if you make changes here. 103 */ 104 /*----------------------------------------------------------------------- 105 * Definitions for initial stack pointer and data area (in DPRAM) 106 */ 107 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 108 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 109 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 110 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 111 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 112 113 /*----------------------------------------------------------------------- 114 * Start addresses for the final memory configuration 115 * (Set up by the startup code) 116 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 117 */ 118 #define CONFIG_SYS_SDRAM_BASE 0x40000000 119 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 120 #define CONFIG_SYS_SDRAM_CFG1 0x53722730 121 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 122 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 123 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 124 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 125 126 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 127 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 128 129 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 130 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 131 132 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 133 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 134 135 /* 136 * For booting Linux, the board info and command line data 137 * have to be in the first 8 MB of memory, since this is 138 * the maximum mapped by the Linux kernel during initialization ?? 139 */ 140 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 141 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 142 143 /*----------------------------------------------------------------------- 144 * FLASH organization 145 */ 146 #define CONFIG_SYS_FLASH_CFI 147 #ifdef CONFIG_SYS_FLASH_CFI 148 # define CONFIG_FLASH_CFI_DRIVER 1 149 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 150 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 151 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 152 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 153 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 154 #endif 155 156 #ifdef CONFIG_NANDFLASH_SIZE 157 # define CONFIG_SYS_MAX_NAND_DEVICE 1 158 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 159 # define CONFIG_SYS_NAND_SIZE 1 160 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 161 # define NAND_ALLOW_ERASE_ALL 1 162 # define CONFIG_JFFS2_NAND 1 163 # define CONFIG_JFFS2_DEV "nand0" 164 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) 165 # define CONFIG_JFFS2_PART_OFFSET 0x00000000 166 #endif 167 168 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 169 170 /* Configuration for environment 171 * Environment is embedded in u-boot in the second sector of the flash 172 */ 173 #define CONFIG_ENV_OFFSET 0x4000 174 #define CONFIG_ENV_SECT_SIZE 0x2000 175 176 #define LDS_BOARD_TEXT \ 177 . = DEFINED(env_offset) ? env_offset : .; \ 178 env/embedded.o(.text*); 179 180 /*----------------------------------------------------------------------- 181 * Cache Configuration 182 */ 183 #define CONFIG_SYS_CACHELINE_SIZE 16 184 185 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 186 CONFIG_SYS_INIT_RAM_SIZE - 8) 187 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 188 CONFIG_SYS_INIT_RAM_SIZE - 4) 189 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 190 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 191 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 192 CF_ACR_EN | CF_ACR_SM_ALL) 193 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 194 CF_CACR_DCM_P) 195 196 /*----------------------------------------------------------------------- 197 * Chipselect bank definitions 198 */ 199 /* 200 * CS0 - NOR Flash 1, 2, 4, or 8MB 201 * CS1 - CompactFlash and registers 202 * CS2 - NAND Flash 16, 32, or 64MB 203 * CS3 - Available 204 * CS4 - Available 205 * CS5 - Available 206 */ 207 #define CONFIG_SYS_CS0_BASE 0 208 #define CONFIG_SYS_CS0_MASK 0x007f0001 209 #define CONFIG_SYS_CS0_CTRL 0x00001fa0 210 211 #define CONFIG_SYS_CS1_BASE 0x10000000 212 #define CONFIG_SYS_CS1_MASK 0x001f0001 213 #define CONFIG_SYS_CS1_CTRL 0x002A3780 214 215 #ifdef CONFIG_NANDFLASH_SIZE 216 #define CONFIG_SYS_CS2_BASE 0x20000000 217 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) 218 #define CONFIG_SYS_CS2_CTRL 0x00001f60 219 #endif 220 221 #endif /* _M5373EVB_H */ 222