1 /* 2 * Configuation settings for the Freescale MCF5373 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef _M5373EVB_H 31 #define _M5373EVB_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_MCF532x /* define processor family */ 38 #define CONFIG_M5373 /* define processor type */ 39 40 #define CONFIG_MCFUART 41 #define CFG_UART_PORT (0) 42 #define CONFIG_BAUDRATE 115200 43 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 44 45 #undef CONFIG_WATCHDOG 46 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ 47 48 /* Command line configuration */ 49 #include <config_cmd_default.h> 50 51 #define CONFIG_CMD_CACHE 52 #define CONFIG_CMD_DATE 53 #define CONFIG_CMD_ELF 54 #define CONFIG_CMD_FLASH 55 #define CONFIG_CMD_I2C 56 #define CONFIG_CMD_MEMORY 57 #define CONFIG_CMD_MISC 58 #define CONFIG_CMD_MII 59 #define CONFIG_CMD_NET 60 #define CONFIG_CMD_PING 61 #define CONFIG_CMD_REGINFO 62 63 #ifdef NANDFLASH_SIZE 64 # define CONFIG_CMD_NAND 65 #endif 66 67 #define CFG_UNIFY_CACHE 68 69 #define CONFIG_MCFFEC 70 #ifdef CONFIG_MCFFEC 71 # define CONFIG_NET_MULTI 1 72 # define CONFIG_MII 1 73 # define CFG_DISCOVER_PHY 74 # define CFG_RX_ETH_BUFFER 8 75 # define CFG_FAULT_ECHO_LINK_DOWN 76 77 # define CFG_FEC0_PINMUX 0 78 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE 79 # define MCFFEC_TOUT_LOOP 50000 80 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ 81 # ifndef CFG_DISCOVER_PHY 82 # define FECDUPLEX FULL 83 # define FECSPEED _100BASET 84 # else 85 # ifndef CFG_FAULT_ECHO_LINK_DOWN 86 # define CFG_FAULT_ECHO_LINK_DOWN 87 # endif 88 # endif /* CFG_DISCOVER_PHY */ 89 #endif 90 91 #define CONFIG_MCFRTC 92 #undef RTC_DEBUG 93 94 /* Timer */ 95 #define CONFIG_MCFTMR 96 #undef CONFIG_MCFPIT 97 98 /* I2C */ 99 #define CONFIG_FSL_I2C 100 #define CONFIG_HARD_I2C /* I2C with hw support */ 101 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 102 #define CFG_I2C_SPEED 80000 103 #define CFG_I2C_SLAVE 0x7F 104 #define CFG_I2C_OFFSET 0x58000 105 #define CFG_IMMR CFG_MBAR 106 107 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 108 #define CONFIG_UDP_CHECKSUM 109 110 #ifdef CONFIG_MCFFEC 111 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 112 # define CONFIG_IPADDR 192.162.1.2 113 # define CONFIG_NETMASK 255.255.255.0 114 # define CONFIG_SERVERIP 192.162.1.1 115 # define CONFIG_GATEWAYIP 192.162.1.1 116 # define CONFIG_OVERWRITE_ETHADDR_ONCE 117 #endif /* FEC_ENET */ 118 119 #define CONFIG_HOSTNAME M5373EVB 120 #define CONFIG_EXTRA_ENV_SETTINGS \ 121 "netdev=eth0\0" \ 122 "loadaddr=" MK_STR(CFG_LOAD_ADDR) "\0" \ 123 "u-boot=u-boot.bin\0" \ 124 "load=tftp ${loadaddr) ${u-boot}\0" \ 125 "upd=run load; run prog\0" \ 126 "prog=prot off 0 2ffff;" \ 127 "era 0 2ffff;" \ 128 "cp.b ${loadaddr} 0 ${filesize};" \ 129 "save\0" \ 130 "" 131 132 #define CONFIG_PRAM 512 /* 512 KB */ 133 #define CFG_PROMPT "-> " 134 #define CFG_LONGHELP /* undef to save memory */ 135 136 #ifdef CONFIG_CMD_KGDB 137 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 138 #else 139 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 140 #endif 141 142 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 143 #define CFG_MAXARGS 16 /* max number of command args */ 144 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 145 #define CFG_LOAD_ADDR 0x40010000 146 147 #define CFG_HZ 1000 148 #define CFG_CLK 80000000 149 #define CFG_CPU_CLK CFG_CLK * 3 150 151 #define CFG_MBAR 0xFC000000 152 153 #define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000) 154 155 /* 156 * Low Level Configuration Settings 157 * (address mappings, register initial values, etc.) 158 * You should know what you are doing if you make changes here. 159 */ 160 /*----------------------------------------------------------------------- 161 * Definitions for initial stack pointer and data area (in DPRAM) 162 */ 163 #define CFG_INIT_RAM_ADDR 0x80000000 164 #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ 165 #define CFG_INIT_RAM_CTRL 0x221 166 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 167 #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10) 168 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 169 170 /*----------------------------------------------------------------------- 171 * Start addresses for the final memory configuration 172 * (Set up by the startup code) 173 * Please note that CFG_SDRAM_BASE _must_ start at 0 174 */ 175 #define CFG_SDRAM_BASE 0x40000000 176 #define CFG_SDRAM_SIZE 32 /* SDRAM size in MB */ 177 #define CFG_SDRAM_CFG1 0x53722730 178 #define CFG_SDRAM_CFG2 0x56670000 179 #define CFG_SDRAM_CTRL 0xE1092000 180 #define CFG_SDRAM_EMOD 0x40010000 181 #define CFG_SDRAM_MODE 0x018D0000 182 183 #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 184 #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) 185 186 #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) 187 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 188 189 #define CFG_BOOTPARAMS_LEN 64*1024 190 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 191 192 /* 193 * For booting Linux, the board info and command line data 194 * have to be in the first 8 MB of memory, since this is 195 * the maximum mapped by the Linux kernel during initialization ?? 196 */ 197 #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) 198 199 /*----------------------------------------------------------------------- 200 * FLASH organization 201 */ 202 #define CFG_FLASH_CFI 203 #ifdef CFG_FLASH_CFI 204 # define CFG_FLASH_CFI_DRIVER 1 205 # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ 206 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT 207 # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ 208 # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 209 # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 210 #endif 211 212 #ifdef NANDFLASH_SIZE 213 # define CFG_MAX_NAND_DEVICE 1 214 # define CFG_NAND_BASE CFG_CS2_BASE 215 # define CFG_NAND_SIZE 1 216 # define CFG_NAND_BASE_LIST { CFG_NAND_BASE } 217 # define NAND_MAX_CHIPS 1 218 # define NAND_ALLOW_ERASE_ALL 1 219 # define CONFIG_JFFS2_NAND 1 220 # define CONFIG_JFFS2_DEV "nand0" 221 # define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1) 222 # define CONFIG_JFFS2_PART_OFFSET 0x00000000 223 #endif 224 225 #define CFG_FLASH_BASE CFG_CS0_BASE 226 227 /* Configuration for environment 228 * Environment is embedded in u-boot in the second sector of the flash 229 */ 230 #define CFG_ENV_OFFSET 0x4000 231 #define CFG_ENV_SECT_SIZE 0x2000 232 #define CFG_ENV_IS_IN_FLASH 1 233 #define CFG_ENV_IS_EMBEDDED 1 234 235 /*----------------------------------------------------------------------- 236 * Cache Configuration 237 */ 238 #define CFG_CACHELINE_SIZE 16 239 240 /*----------------------------------------------------------------------- 241 * Chipselect bank definitions 242 */ 243 /* 244 * CS0 - NOR Flash 1, 2, 4, or 8MB 245 * CS1 - CompactFlash and registers 246 * CS2 - NAND Flash 16, 32, or 64MB 247 * CS3 - Available 248 * CS4 - Available 249 * CS5 - Available 250 */ 251 #define CFG_CS0_BASE 0 252 #define CFG_CS0_MASK 0x007f0001 253 #define CFG_CS0_CTRL 0x00001fa0 254 255 #define CFG_CS1_BASE 0x10000000 256 #define CFG_CS1_MASK 0x001f0001 257 #define CFG_CS1_CTRL 0x002A3780 258 259 #ifdef NANDFLASH_SIZE 260 #define CFG_CS2_BASE 0x20000000 261 #define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1) 262 #define CFG_CS2_CTRL 0x00001f60 263 #endif 264 265 #endif /* _M5373EVB_H */ 266