1 /* 2 * Configuation settings for the Freescale MCF5373 FireEngine board. 3 * 4 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5373EVB_H 15 #define _M5373EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ 27 28 /* Command line configuration */ 29 #define CONFIG_CMD_REGINFO 30 31 #ifdef CONFIG_NANDFLASH_SIZE 32 # define CONFIG_CMD_NAND 33 #endif 34 35 #define CONFIG_SYS_UNIFY_CACHE 36 37 #define CONFIG_MCFFEC 38 #ifdef CONFIG_MCFFEC 39 # define CONFIG_MII 1 40 # define CONFIG_MII_INIT 1 41 # define CONFIG_SYS_DISCOVER_PHY 42 # define CONFIG_SYS_RX_ETH_BUFFER 8 43 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 44 45 # define CONFIG_SYS_FEC0_PINMUX 0 46 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 47 # define MCFFEC_TOUT_LOOP 50000 48 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 49 # ifndef CONFIG_SYS_DISCOVER_PHY 50 # define FECDUPLEX FULL 51 # define FECSPEED _100BASET 52 # else 53 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 54 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 55 # endif 56 # endif /* CONFIG_SYS_DISCOVER_PHY */ 57 #endif 58 59 #define CONFIG_MCFRTC 60 #undef RTC_DEBUG 61 62 /* Timer */ 63 #define CONFIG_MCFTMR 64 #undef CONFIG_MCFPIT 65 66 /* I2C */ 67 #define CONFIG_SYS_I2C 68 #define CONFIG_SYS_I2C_FSL 69 #define CONFIG_SYS_FSL_I2C_SPEED 80000 70 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 71 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 72 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 73 74 #define CONFIG_UDP_CHECKSUM 75 76 #ifdef CONFIG_MCFFEC 77 # define CONFIG_IPADDR 192.162.1.2 78 # define CONFIG_NETMASK 255.255.255.0 79 # define CONFIG_SERVERIP 192.162.1.1 80 # define CONFIG_GATEWAYIP 192.162.1.1 81 #endif /* FEC_ENET */ 82 83 #define CONFIG_HOSTNAME M5373EVB 84 #define CONFIG_EXTRA_ENV_SETTINGS \ 85 "netdev=eth0\0" \ 86 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 87 "u-boot=u-boot.bin\0" \ 88 "load=tftp ${loadaddr) ${u-boot}\0" \ 89 "upd=run load; run prog\0" \ 90 "prog=prot off 0 3ffff;" \ 91 "era 0 3ffff;" \ 92 "cp.b ${loadaddr} 0 ${filesize};" \ 93 "save\0" \ 94 "" 95 96 #define CONFIG_PRAM 512 /* 512 KB */ 97 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 98 99 #ifdef CONFIG_CMD_KGDB 100 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 101 #else 102 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 103 #endif 104 105 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 106 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 107 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 108 #define CONFIG_SYS_LOAD_ADDR 0x40010000 109 110 #define CONFIG_SYS_CLK 80000000 111 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 112 113 #define CONFIG_SYS_MBAR 0xFC000000 114 115 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 116 117 /* 118 * Low Level Configuration Settings 119 * (address mappings, register initial values, etc.) 120 * You should know what you are doing if you make changes here. 121 */ 122 /*----------------------------------------------------------------------- 123 * Definitions for initial stack pointer and data area (in DPRAM) 124 */ 125 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 126 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 127 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 128 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 129 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 130 131 /*----------------------------------------------------------------------- 132 * Start addresses for the final memory configuration 133 * (Set up by the startup code) 134 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 135 */ 136 #define CONFIG_SYS_SDRAM_BASE 0x40000000 137 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 138 #define CONFIG_SYS_SDRAM_CFG1 0x53722730 139 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 140 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 141 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 142 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 143 144 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 145 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 146 147 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 148 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 149 150 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 151 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 152 153 /* 154 * For booting Linux, the board info and command line data 155 * have to be in the first 8 MB of memory, since this is 156 * the maximum mapped by the Linux kernel during initialization ?? 157 */ 158 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 159 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 160 161 /*----------------------------------------------------------------------- 162 * FLASH organization 163 */ 164 #define CONFIG_SYS_FLASH_CFI 165 #ifdef CONFIG_SYS_FLASH_CFI 166 # define CONFIG_FLASH_CFI_DRIVER 1 167 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 168 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 169 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 170 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 171 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 172 #endif 173 174 #ifdef CONFIG_NANDFLASH_SIZE 175 # define CONFIG_SYS_MAX_NAND_DEVICE 1 176 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 177 # define CONFIG_SYS_NAND_SIZE 1 178 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 179 # define NAND_ALLOW_ERASE_ALL 1 180 # define CONFIG_JFFS2_NAND 1 181 # define CONFIG_JFFS2_DEV "nand0" 182 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) 183 # define CONFIG_JFFS2_PART_OFFSET 0x00000000 184 #endif 185 186 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 187 188 /* Configuration for environment 189 * Environment is embedded in u-boot in the second sector of the flash 190 */ 191 #define CONFIG_ENV_OFFSET 0x4000 192 #define CONFIG_ENV_SECT_SIZE 0x2000 193 #define CONFIG_ENV_IS_IN_FLASH 1 194 195 #define LDS_BOARD_TEXT \ 196 . = DEFINED(env_offset) ? env_offset : .; \ 197 common/env_embedded.o (.text*); 198 199 /*----------------------------------------------------------------------- 200 * Cache Configuration 201 */ 202 #define CONFIG_SYS_CACHELINE_SIZE 16 203 204 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 205 CONFIG_SYS_INIT_RAM_SIZE - 8) 206 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 207 CONFIG_SYS_INIT_RAM_SIZE - 4) 208 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 209 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 210 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 211 CF_ACR_EN | CF_ACR_SM_ALL) 212 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 213 CF_CACR_DCM_P) 214 215 /*----------------------------------------------------------------------- 216 * Chipselect bank definitions 217 */ 218 /* 219 * CS0 - NOR Flash 1, 2, 4, or 8MB 220 * CS1 - CompactFlash and registers 221 * CS2 - NAND Flash 16, 32, or 64MB 222 * CS3 - Available 223 * CS4 - Available 224 * CS5 - Available 225 */ 226 #define CONFIG_SYS_CS0_BASE 0 227 #define CONFIG_SYS_CS0_MASK 0x007f0001 228 #define CONFIG_SYS_CS0_CTRL 0x00001fa0 229 230 #define CONFIG_SYS_CS1_BASE 0x10000000 231 #define CONFIG_SYS_CS1_MASK 0x001f0001 232 #define CONFIG_SYS_CS1_CTRL 0x002A3780 233 234 #ifdef CONFIG_NANDFLASH_SIZE 235 #define CONFIG_SYS_CS2_BASE 0x20000000 236 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) 237 #define CONFIG_SYS_CS2_CTRL 0x00001f60 238 #endif 239 240 #endif /* _M5373EVB_H */ 241