1 /* 2 * Configuation settings for the Freescale MCF5373 FireEngine board. 3 * 4 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5373EVB_H 15 #define _M5373EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 #define CONFIG_BAUDRATE 115200 25 26 #undef CONFIG_WATCHDOG 27 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ 28 29 /* Command line configuration */ 30 #include <config_cmd_default.h> 31 32 #define CONFIG_CMD_CACHE 33 #define CONFIG_CMD_DATE 34 #define CONFIG_CMD_ELF 35 #define CONFIG_CMD_FLASH 36 #define CONFIG_CMD_I2C 37 #define CONFIG_CMD_MEMORY 38 #define CONFIG_CMD_MISC 39 #define CONFIG_CMD_MII 40 #define CONFIG_CMD_PING 41 #define CONFIG_CMD_REGINFO 42 43 #ifdef CONFIG_NANDFLASH_SIZE 44 # define CONFIG_CMD_NAND 45 #endif 46 47 #define CONFIG_SYS_UNIFY_CACHE 48 49 #define CONFIG_MCFFEC 50 #ifdef CONFIG_MCFFEC 51 # define CONFIG_MII 1 52 # define CONFIG_MII_INIT 1 53 # define CONFIG_SYS_DISCOVER_PHY 54 # define CONFIG_SYS_RX_ETH_BUFFER 8 55 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 56 57 # define CONFIG_SYS_FEC0_PINMUX 0 58 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 59 # define MCFFEC_TOUT_LOOP 50000 60 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 61 # ifndef CONFIG_SYS_DISCOVER_PHY 62 # define FECDUPLEX FULL 63 # define FECSPEED _100BASET 64 # else 65 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 66 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 67 # endif 68 # endif /* CONFIG_SYS_DISCOVER_PHY */ 69 #endif 70 71 #define CONFIG_MCFRTC 72 #undef RTC_DEBUG 73 74 /* Timer */ 75 #define CONFIG_MCFTMR 76 #undef CONFIG_MCFPIT 77 78 /* I2C */ 79 #define CONFIG_SYS_I2C 80 #define CONFIG_SYS_I2C_FSL 81 #define CONFIG_SYS_FSL_I2C_SPEED 80000 82 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 83 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 84 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 85 86 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 87 #define CONFIG_UDP_CHECKSUM 88 89 #ifdef CONFIG_MCFFEC 90 # define CONFIG_IPADDR 192.162.1.2 91 # define CONFIG_NETMASK 255.255.255.0 92 # define CONFIG_SERVERIP 192.162.1.1 93 # define CONFIG_GATEWAYIP 192.162.1.1 94 #endif /* FEC_ENET */ 95 96 #define CONFIG_HOSTNAME M5373EVB 97 #define CONFIG_EXTRA_ENV_SETTINGS \ 98 "netdev=eth0\0" \ 99 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 100 "u-boot=u-boot.bin\0" \ 101 "load=tftp ${loadaddr) ${u-boot}\0" \ 102 "upd=run load; run prog\0" \ 103 "prog=prot off 0 3ffff;" \ 104 "era 0 3ffff;" \ 105 "cp.b ${loadaddr} 0 ${filesize};" \ 106 "save\0" \ 107 "" 108 109 #define CONFIG_PRAM 512 /* 512 KB */ 110 #define CONFIG_SYS_PROMPT "-> " 111 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 112 113 #ifdef CONFIG_CMD_KGDB 114 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 115 #else 116 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 117 #endif 118 119 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 120 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 121 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 122 #define CONFIG_SYS_LOAD_ADDR 0x40010000 123 124 #define CONFIG_SYS_CLK 80000000 125 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 126 127 #define CONFIG_SYS_MBAR 0xFC000000 128 129 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 130 131 /* 132 * Low Level Configuration Settings 133 * (address mappings, register initial values, etc.) 134 * You should know what you are doing if you make changes here. 135 */ 136 /*----------------------------------------------------------------------- 137 * Definitions for initial stack pointer and data area (in DPRAM) 138 */ 139 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 140 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 141 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 142 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 143 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 144 145 /*----------------------------------------------------------------------- 146 * Start addresses for the final memory configuration 147 * (Set up by the startup code) 148 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 149 */ 150 #define CONFIG_SYS_SDRAM_BASE 0x40000000 151 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 152 #define CONFIG_SYS_SDRAM_CFG1 0x53722730 153 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 154 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 155 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 156 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 157 158 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 159 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 160 161 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 162 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 163 164 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 165 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 166 167 /* 168 * For booting Linux, the board info and command line data 169 * have to be in the first 8 MB of memory, since this is 170 * the maximum mapped by the Linux kernel during initialization ?? 171 */ 172 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 173 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 174 175 /*----------------------------------------------------------------------- 176 * FLASH organization 177 */ 178 #define CONFIG_SYS_FLASH_CFI 179 #ifdef CONFIG_SYS_FLASH_CFI 180 # define CONFIG_FLASH_CFI_DRIVER 1 181 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 182 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 183 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 184 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 185 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 186 #endif 187 188 #ifdef CONFIG_NANDFLASH_SIZE 189 # define CONFIG_SYS_MAX_NAND_DEVICE 1 190 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 191 # define CONFIG_SYS_NAND_SIZE 1 192 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 193 # define NAND_ALLOW_ERASE_ALL 1 194 # define CONFIG_JFFS2_NAND 1 195 # define CONFIG_JFFS2_DEV "nand0" 196 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) 197 # define CONFIG_JFFS2_PART_OFFSET 0x00000000 198 #endif 199 200 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 201 202 /* Configuration for environment 203 * Environment is embedded in u-boot in the second sector of the flash 204 */ 205 #define CONFIG_ENV_OFFSET 0x4000 206 #define CONFIG_ENV_SECT_SIZE 0x2000 207 #define CONFIG_ENV_IS_IN_FLASH 1 208 209 #define LDS_BOARD_TEXT \ 210 . = DEFINED(env_offset) ? env_offset : .; \ 211 common/env_embedded.o (.text*); 212 213 /*----------------------------------------------------------------------- 214 * Cache Configuration 215 */ 216 #define CONFIG_SYS_CACHELINE_SIZE 16 217 218 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 219 CONFIG_SYS_INIT_RAM_SIZE - 8) 220 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 221 CONFIG_SYS_INIT_RAM_SIZE - 4) 222 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 223 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 224 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 225 CF_ACR_EN | CF_ACR_SM_ALL) 226 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 227 CF_CACR_DCM_P) 228 229 /*----------------------------------------------------------------------- 230 * Chipselect bank definitions 231 */ 232 /* 233 * CS0 - NOR Flash 1, 2, 4, or 8MB 234 * CS1 - CompactFlash and registers 235 * CS2 - NAND Flash 16, 32, or 64MB 236 * CS3 - Available 237 * CS4 - Available 238 * CS5 - Available 239 */ 240 #define CONFIG_SYS_CS0_BASE 0 241 #define CONFIG_SYS_CS0_MASK 0x007f0001 242 #define CONFIG_SYS_CS0_CTRL 0x00001fa0 243 244 #define CONFIG_SYS_CS1_BASE 0x10000000 245 #define CONFIG_SYS_CS1_MASK 0x001f0001 246 #define CONFIG_SYS_CS1_CTRL 0x002A3780 247 248 #ifdef CONFIG_NANDFLASH_SIZE 249 #define CONFIG_SYS_CS2_BASE 0x20000000 250 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) 251 #define CONFIG_SYS_CS2_CTRL 0x00001f60 252 #endif 253 254 #endif /* _M5373EVB_H */ 255