1 /* 2 * Configuation settings for the Freescale MCF5373 FireEngine board. 3 * 4 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5373EVB_H 15 #define _M5373EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 #define CONFIG_BAUDRATE 115200 25 26 #undef CONFIG_WATCHDOG 27 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ 28 29 /* Command line configuration */ 30 #define CONFIG_CMD_CACHE 31 #define CONFIG_CMD_DATE 32 #define CONFIG_CMD_I2C 33 #define CONFIG_CMD_MII 34 #define CONFIG_CMD_PING 35 #define CONFIG_CMD_REGINFO 36 37 #ifdef CONFIG_NANDFLASH_SIZE 38 # define CONFIG_CMD_NAND 39 #endif 40 41 #define CONFIG_SYS_UNIFY_CACHE 42 43 #define CONFIG_MCFFEC 44 #ifdef CONFIG_MCFFEC 45 # define CONFIG_MII 1 46 # define CONFIG_MII_INIT 1 47 # define CONFIG_SYS_DISCOVER_PHY 48 # define CONFIG_SYS_RX_ETH_BUFFER 8 49 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 50 51 # define CONFIG_SYS_FEC0_PINMUX 0 52 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 53 # define MCFFEC_TOUT_LOOP 50000 54 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 55 # ifndef CONFIG_SYS_DISCOVER_PHY 56 # define FECDUPLEX FULL 57 # define FECSPEED _100BASET 58 # else 59 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 60 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 61 # endif 62 # endif /* CONFIG_SYS_DISCOVER_PHY */ 63 #endif 64 65 #define CONFIG_MCFRTC 66 #undef RTC_DEBUG 67 68 /* Timer */ 69 #define CONFIG_MCFTMR 70 #undef CONFIG_MCFPIT 71 72 /* I2C */ 73 #define CONFIG_SYS_I2C 74 #define CONFIG_SYS_I2C_FSL 75 #define CONFIG_SYS_FSL_I2C_SPEED 80000 76 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 77 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 78 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 79 80 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 81 #define CONFIG_UDP_CHECKSUM 82 83 #ifdef CONFIG_MCFFEC 84 # define CONFIG_IPADDR 192.162.1.2 85 # define CONFIG_NETMASK 255.255.255.0 86 # define CONFIG_SERVERIP 192.162.1.1 87 # define CONFIG_GATEWAYIP 192.162.1.1 88 #endif /* FEC_ENET */ 89 90 #define CONFIG_HOSTNAME M5373EVB 91 #define CONFIG_EXTRA_ENV_SETTINGS \ 92 "netdev=eth0\0" \ 93 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 94 "u-boot=u-boot.bin\0" \ 95 "load=tftp ${loadaddr) ${u-boot}\0" \ 96 "upd=run load; run prog\0" \ 97 "prog=prot off 0 3ffff;" \ 98 "era 0 3ffff;" \ 99 "cp.b ${loadaddr} 0 ${filesize};" \ 100 "save\0" \ 101 "" 102 103 #define CONFIG_PRAM 512 /* 512 KB */ 104 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 105 106 #ifdef CONFIG_CMD_KGDB 107 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 108 #else 109 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 110 #endif 111 112 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 113 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 114 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 115 #define CONFIG_SYS_LOAD_ADDR 0x40010000 116 117 #define CONFIG_SYS_CLK 80000000 118 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 119 120 #define CONFIG_SYS_MBAR 0xFC000000 121 122 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 123 124 /* 125 * Low Level Configuration Settings 126 * (address mappings, register initial values, etc.) 127 * You should know what you are doing if you make changes here. 128 */ 129 /*----------------------------------------------------------------------- 130 * Definitions for initial stack pointer and data area (in DPRAM) 131 */ 132 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 133 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 134 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 135 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 136 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 137 138 /*----------------------------------------------------------------------- 139 * Start addresses for the final memory configuration 140 * (Set up by the startup code) 141 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 142 */ 143 #define CONFIG_SYS_SDRAM_BASE 0x40000000 144 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 145 #define CONFIG_SYS_SDRAM_CFG1 0x53722730 146 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 147 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 148 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 149 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 150 151 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 152 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 153 154 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 155 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 156 157 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 158 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 159 160 /* 161 * For booting Linux, the board info and command line data 162 * have to be in the first 8 MB of memory, since this is 163 * the maximum mapped by the Linux kernel during initialization ?? 164 */ 165 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 166 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 167 168 /*----------------------------------------------------------------------- 169 * FLASH organization 170 */ 171 #define CONFIG_SYS_FLASH_CFI 172 #ifdef CONFIG_SYS_FLASH_CFI 173 # define CONFIG_FLASH_CFI_DRIVER 1 174 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 175 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 176 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 177 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 178 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 179 #endif 180 181 #ifdef CONFIG_NANDFLASH_SIZE 182 # define CONFIG_SYS_MAX_NAND_DEVICE 1 183 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 184 # define CONFIG_SYS_NAND_SIZE 1 185 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 186 # define NAND_ALLOW_ERASE_ALL 1 187 # define CONFIG_JFFS2_NAND 1 188 # define CONFIG_JFFS2_DEV "nand0" 189 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) 190 # define CONFIG_JFFS2_PART_OFFSET 0x00000000 191 #endif 192 193 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 194 195 /* Configuration for environment 196 * Environment is embedded in u-boot in the second sector of the flash 197 */ 198 #define CONFIG_ENV_OFFSET 0x4000 199 #define CONFIG_ENV_SECT_SIZE 0x2000 200 #define CONFIG_ENV_IS_IN_FLASH 1 201 202 #define LDS_BOARD_TEXT \ 203 . = DEFINED(env_offset) ? env_offset : .; \ 204 common/env_embedded.o (.text*); 205 206 /*----------------------------------------------------------------------- 207 * Cache Configuration 208 */ 209 #define CONFIG_SYS_CACHELINE_SIZE 16 210 211 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 212 CONFIG_SYS_INIT_RAM_SIZE - 8) 213 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 214 CONFIG_SYS_INIT_RAM_SIZE - 4) 215 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 216 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 217 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 218 CF_ACR_EN | CF_ACR_SM_ALL) 219 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 220 CF_CACR_DCM_P) 221 222 /*----------------------------------------------------------------------- 223 * Chipselect bank definitions 224 */ 225 /* 226 * CS0 - NOR Flash 1, 2, 4, or 8MB 227 * CS1 - CompactFlash and registers 228 * CS2 - NAND Flash 16, 32, or 64MB 229 * CS3 - Available 230 * CS4 - Available 231 * CS5 - Available 232 */ 233 #define CONFIG_SYS_CS0_BASE 0 234 #define CONFIG_SYS_CS0_MASK 0x007f0001 235 #define CONFIG_SYS_CS0_CTRL 0x00001fa0 236 237 #define CONFIG_SYS_CS1_BASE 0x10000000 238 #define CONFIG_SYS_CS1_MASK 0x001f0001 239 #define CONFIG_SYS_CS1_CTRL 0x002A3780 240 241 #ifdef CONFIG_NANDFLASH_SIZE 242 #define CONFIG_SYS_CS2_BASE 0x20000000 243 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) 244 #define CONFIG_SYS_CS2_CTRL 0x00001f60 245 #endif 246 247 #endif /* _M5373EVB_H */ 248