1 /* 2 * Configuation settings for the Freescale MCF5373 FireEngine board. 3 * 4 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5373EVB_H 15 #define _M5373EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ 27 28 #define CONFIG_SYS_UNIFY_CACHE 29 30 #define CONFIG_MCFFEC 31 #ifdef CONFIG_MCFFEC 32 # define CONFIG_MII 1 33 # define CONFIG_MII_INIT 1 34 # define CONFIG_SYS_DISCOVER_PHY 35 # define CONFIG_SYS_RX_ETH_BUFFER 8 36 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 37 38 # define CONFIG_SYS_FEC0_PINMUX 0 39 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 40 # define MCFFEC_TOUT_LOOP 50000 41 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 42 # ifndef CONFIG_SYS_DISCOVER_PHY 43 # define FECDUPLEX FULL 44 # define FECSPEED _100BASET 45 # else 46 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 47 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 48 # endif 49 # endif /* CONFIG_SYS_DISCOVER_PHY */ 50 #endif 51 52 #define CONFIG_MCFRTC 53 #undef RTC_DEBUG 54 55 /* Timer */ 56 #define CONFIG_MCFTMR 57 #undef CONFIG_MCFPIT 58 59 /* I2C */ 60 #define CONFIG_SYS_I2C 61 #define CONFIG_SYS_I2C_FSL 62 #define CONFIG_SYS_FSL_I2C_SPEED 80000 63 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 64 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 65 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 66 67 #define CONFIG_UDP_CHECKSUM 68 69 #ifdef CONFIG_MCFFEC 70 # define CONFIG_IPADDR 192.162.1.2 71 # define CONFIG_NETMASK 255.255.255.0 72 # define CONFIG_SERVERIP 192.162.1.1 73 # define CONFIG_GATEWAYIP 192.162.1.1 74 #endif /* FEC_ENET */ 75 76 #define CONFIG_HOSTNAME "M5373EVB" 77 #define CONFIG_EXTRA_ENV_SETTINGS \ 78 "netdev=eth0\0" \ 79 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 80 "u-boot=u-boot.bin\0" \ 81 "load=tftp ${loadaddr) ${u-boot}\0" \ 82 "upd=run load; run prog\0" \ 83 "prog=prot off 0 3ffff;" \ 84 "era 0 3ffff;" \ 85 "cp.b ${loadaddr} 0 ${filesize};" \ 86 "save\0" \ 87 "" 88 89 #define CONFIG_PRAM 512 /* 512 KB */ 90 91 #define CONFIG_SYS_LOAD_ADDR 0x40010000 92 93 #define CONFIG_SYS_CLK 80000000 94 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 95 96 #define CONFIG_SYS_MBAR 0xFC000000 97 98 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 99 100 /* 101 * Low Level Configuration Settings 102 * (address mappings, register initial values, etc.) 103 * You should know what you are doing if you make changes here. 104 */ 105 /*----------------------------------------------------------------------- 106 * Definitions for initial stack pointer and data area (in DPRAM) 107 */ 108 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 109 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 110 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 111 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 112 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 113 114 /*----------------------------------------------------------------------- 115 * Start addresses for the final memory configuration 116 * (Set up by the startup code) 117 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 118 */ 119 #define CONFIG_SYS_SDRAM_BASE 0x40000000 120 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 121 #define CONFIG_SYS_SDRAM_CFG1 0x53722730 122 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 123 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 124 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 125 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 126 127 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 128 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 129 130 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 131 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 132 133 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 134 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 135 136 /* 137 * For booting Linux, the board info and command line data 138 * have to be in the first 8 MB of memory, since this is 139 * the maximum mapped by the Linux kernel during initialization ?? 140 */ 141 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 142 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 143 144 /*----------------------------------------------------------------------- 145 * FLASH organization 146 */ 147 #define CONFIG_SYS_FLASH_CFI 148 #ifdef CONFIG_SYS_FLASH_CFI 149 # define CONFIG_FLASH_CFI_DRIVER 1 150 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 151 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 152 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 153 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 154 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 155 #endif 156 157 #ifdef CONFIG_NANDFLASH_SIZE 158 # define CONFIG_SYS_MAX_NAND_DEVICE 1 159 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 160 # define CONFIG_SYS_NAND_SIZE 1 161 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 162 # define NAND_ALLOW_ERASE_ALL 1 163 # define CONFIG_JFFS2_NAND 1 164 # define CONFIG_JFFS2_DEV "nand0" 165 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) 166 # define CONFIG_JFFS2_PART_OFFSET 0x00000000 167 #endif 168 169 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 170 171 /* Configuration for environment 172 * Environment is embedded in u-boot in the second sector of the flash 173 */ 174 #define CONFIG_ENV_OFFSET 0x4000 175 #define CONFIG_ENV_SECT_SIZE 0x2000 176 177 #define LDS_BOARD_TEXT \ 178 . = DEFINED(env_offset) ? env_offset : .; \ 179 env/embedded.o(.text*); 180 181 /*----------------------------------------------------------------------- 182 * Cache Configuration 183 */ 184 #define CONFIG_SYS_CACHELINE_SIZE 16 185 186 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 187 CONFIG_SYS_INIT_RAM_SIZE - 8) 188 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 189 CONFIG_SYS_INIT_RAM_SIZE - 4) 190 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 191 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 192 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 193 CF_ACR_EN | CF_ACR_SM_ALL) 194 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 195 CF_CACR_DCM_P) 196 197 /*----------------------------------------------------------------------- 198 * Chipselect bank definitions 199 */ 200 /* 201 * CS0 - NOR Flash 1, 2, 4, or 8MB 202 * CS1 - CompactFlash and registers 203 * CS2 - NAND Flash 16, 32, or 64MB 204 * CS3 - Available 205 * CS4 - Available 206 * CS5 - Available 207 */ 208 #define CONFIG_SYS_CS0_BASE 0 209 #define CONFIG_SYS_CS0_MASK 0x007f0001 210 #define CONFIG_SYS_CS0_CTRL 0x00001fa0 211 212 #define CONFIG_SYS_CS1_BASE 0x10000000 213 #define CONFIG_SYS_CS1_MASK 0x001f0001 214 #define CONFIG_SYS_CS1_CTRL 0x002A3780 215 216 #ifdef CONFIG_NANDFLASH_SIZE 217 #define CONFIG_SYS_CS2_BASE 0x20000000 218 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) 219 #define CONFIG_SYS_CS2_CTRL 0x00001f60 220 #endif 221 222 #endif /* _M5373EVB_H */ 223