1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Freescale MCF5373 FireEngine board. 4 * 5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M5373EVB_H 14 #define _M5373EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21 #define CONFIG_MCFUART 22 #define CONFIG_SYS_UART_PORT (0) 23 24 #undef CONFIG_WATCHDOG 25 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ 26 27 #define CONFIG_SYS_UNIFY_CACHE 28 29 #define CONFIG_MCFFEC 30 #ifdef CONFIG_MCFFEC 31 # define CONFIG_MII_INIT 1 32 # define CONFIG_SYS_DISCOVER_PHY 33 # define CONFIG_SYS_RX_ETH_BUFFER 8 34 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 35 36 # define CONFIG_SYS_FEC0_PINMUX 0 37 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 38 # define MCFFEC_TOUT_LOOP 50000 39 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 40 # ifndef CONFIG_SYS_DISCOVER_PHY 41 # define FECDUPLEX FULL 42 # define FECSPEED _100BASET 43 # else 44 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 45 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 46 # endif 47 # endif /* CONFIG_SYS_DISCOVER_PHY */ 48 #endif 49 50 #define CONFIG_MCFRTC 51 #undef RTC_DEBUG 52 53 /* Timer */ 54 #define CONFIG_MCFTMR 55 #undef CONFIG_MCFPIT 56 57 /* I2C */ 58 #define CONFIG_SYS_I2C 59 #define CONFIG_SYS_I2C_FSL 60 #define CONFIG_SYS_FSL_I2C_SPEED 80000 61 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 62 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 63 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 64 65 #define CONFIG_UDP_CHECKSUM 66 67 #ifdef CONFIG_MCFFEC 68 # define CONFIG_IPADDR 192.162.1.2 69 # define CONFIG_NETMASK 255.255.255.0 70 # define CONFIG_SERVERIP 192.162.1.1 71 # define CONFIG_GATEWAYIP 192.162.1.1 72 #endif /* FEC_ENET */ 73 74 #define CONFIG_HOSTNAME "M5373EVB" 75 #define CONFIG_EXTRA_ENV_SETTINGS \ 76 "netdev=eth0\0" \ 77 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 78 "u-boot=u-boot.bin\0" \ 79 "load=tftp ${loadaddr) ${u-boot}\0" \ 80 "upd=run load; run prog\0" \ 81 "prog=prot off 0 3ffff;" \ 82 "era 0 3ffff;" \ 83 "cp.b ${loadaddr} 0 ${filesize};" \ 84 "save\0" \ 85 "" 86 87 #define CONFIG_PRAM 512 /* 512 KB */ 88 89 #define CONFIG_SYS_LOAD_ADDR 0x40010000 90 91 #define CONFIG_SYS_CLK 80000000 92 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 93 94 #define CONFIG_SYS_MBAR 0xFC000000 95 96 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 97 98 /* 99 * Low Level Configuration Settings 100 * (address mappings, register initial values, etc.) 101 * You should know what you are doing if you make changes here. 102 */ 103 /*----------------------------------------------------------------------- 104 * Definitions for initial stack pointer and data area (in DPRAM) 105 */ 106 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 107 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 108 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 109 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 110 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 111 112 /*----------------------------------------------------------------------- 113 * Start addresses for the final memory configuration 114 * (Set up by the startup code) 115 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 116 */ 117 #define CONFIG_SYS_SDRAM_BASE 0x40000000 118 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 119 #define CONFIG_SYS_SDRAM_CFG1 0x53722730 120 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 121 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 122 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 123 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 124 125 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 126 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 127 128 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 129 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 130 131 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 132 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 133 134 /* 135 * For booting Linux, the board info and command line data 136 * have to be in the first 8 MB of memory, since this is 137 * the maximum mapped by the Linux kernel during initialization ?? 138 */ 139 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 140 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 141 142 /*----------------------------------------------------------------------- 143 * FLASH organization 144 */ 145 #define CONFIG_SYS_FLASH_CFI 146 #ifdef CONFIG_SYS_FLASH_CFI 147 # define CONFIG_FLASH_CFI_DRIVER 1 148 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 149 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 150 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 151 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 152 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 153 #endif 154 155 #ifdef CONFIG_NANDFLASH_SIZE 156 # define CONFIG_SYS_MAX_NAND_DEVICE 1 157 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 158 # define CONFIG_SYS_NAND_SIZE 1 159 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 160 # define NAND_ALLOW_ERASE_ALL 1 161 # define CONFIG_JFFS2_NAND 1 162 # define CONFIG_JFFS2_DEV "nand0" 163 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) 164 # define CONFIG_JFFS2_PART_OFFSET 0x00000000 165 #endif 166 167 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 168 169 /* Configuration for environment 170 * Environment is embedded in u-boot in the second sector of the flash 171 */ 172 #define CONFIG_ENV_OFFSET 0x4000 173 #define CONFIG_ENV_SECT_SIZE 0x2000 174 175 #define LDS_BOARD_TEXT \ 176 . = DEFINED(env_offset) ? env_offset : .; \ 177 env/embedded.o(.text*); 178 179 /*----------------------------------------------------------------------- 180 * Cache Configuration 181 */ 182 #define CONFIG_SYS_CACHELINE_SIZE 16 183 184 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 185 CONFIG_SYS_INIT_RAM_SIZE - 8) 186 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 187 CONFIG_SYS_INIT_RAM_SIZE - 4) 188 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 189 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 190 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 191 CF_ACR_EN | CF_ACR_SM_ALL) 192 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 193 CF_CACR_DCM_P) 194 195 /*----------------------------------------------------------------------- 196 * Chipselect bank definitions 197 */ 198 /* 199 * CS0 - NOR Flash 1, 2, 4, or 8MB 200 * CS1 - CompactFlash and registers 201 * CS2 - NAND Flash 16, 32, or 64MB 202 * CS3 - Available 203 * CS4 - Available 204 * CS5 - Available 205 */ 206 #define CONFIG_SYS_CS0_BASE 0 207 #define CONFIG_SYS_CS0_MASK 0x007f0001 208 #define CONFIG_SYS_CS0_CTRL 0x00001fa0 209 210 #define CONFIG_SYS_CS1_BASE 0x10000000 211 #define CONFIG_SYS_CS1_MASK 0x001f0001 212 #define CONFIG_SYS_CS1_CTRL 0x002A3780 213 214 #ifdef CONFIG_NANDFLASH_SIZE 215 #define CONFIG_SYS_CS2_BASE 0x20000000 216 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) 217 #define CONFIG_SYS_CS2_CTRL 0x00001f60 218 #endif 219 220 #endif /* _M5373EVB_H */ 221