1 /* 2 * Configuation settings for the Freescale MCF5373 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef _M5373EVB_H 31 #define _M5373EVB_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_MCF532x /* define processor family */ 38 #define CONFIG_M5373 /* define processor type */ 39 40 #define CONFIG_MCFUART 41 #define CONFIG_SYS_UART_PORT (0) 42 #define CONFIG_BAUDRATE 115200 43 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 44 45 #undef CONFIG_WATCHDOG 46 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ 47 48 /* Command line configuration */ 49 #include <config_cmd_default.h> 50 51 #define CONFIG_CMD_CACHE 52 #define CONFIG_CMD_DATE 53 #define CONFIG_CMD_ELF 54 #define CONFIG_CMD_FLASH 55 #define CONFIG_CMD_I2C 56 #define CONFIG_CMD_MEMORY 57 #define CONFIG_CMD_MISC 58 #define CONFIG_CMD_MII 59 #define CONFIG_CMD_NET 60 #define CONFIG_CMD_PING 61 #define CONFIG_CMD_REGINFO 62 63 #ifdef NANDFLASH_SIZE 64 # define CONFIG_CMD_NAND 65 #endif 66 67 #define CONFIG_SYS_UNIFY_CACHE 68 69 #define CONFIG_MCFFEC 70 #ifdef CONFIG_MCFFEC 71 # define CONFIG_MII 1 72 # define CONFIG_MII_INIT 1 73 # define CONFIG_SYS_DISCOVER_PHY 74 # define CONFIG_SYS_RX_ETH_BUFFER 8 75 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 76 77 # define CONFIG_SYS_FEC0_PINMUX 0 78 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 79 # define MCFFEC_TOUT_LOOP 50000 80 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 81 # ifndef CONFIG_SYS_DISCOVER_PHY 82 # define FECDUPLEX FULL 83 # define FECSPEED _100BASET 84 # else 85 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 86 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 87 # endif 88 # endif /* CONFIG_SYS_DISCOVER_PHY */ 89 #endif 90 91 #define CONFIG_MCFRTC 92 #undef RTC_DEBUG 93 94 /* Timer */ 95 #define CONFIG_MCFTMR 96 #undef CONFIG_MCFPIT 97 98 /* I2C */ 99 #define CONFIG_FSL_I2C 100 #define CONFIG_HARD_I2C /* I2C with hw support */ 101 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 102 #define CONFIG_SYS_I2C_SPEED 80000 103 #define CONFIG_SYS_I2C_SLAVE 0x7F 104 #define CONFIG_SYS_I2C_OFFSET 0x58000 105 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 106 107 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 108 #define CONFIG_UDP_CHECKSUM 109 110 #ifdef CONFIG_MCFFEC 111 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 112 # define CONFIG_IPADDR 192.162.1.2 113 # define CONFIG_NETMASK 255.255.255.0 114 # define CONFIG_SERVERIP 192.162.1.1 115 # define CONFIG_GATEWAYIP 192.162.1.1 116 # define CONFIG_OVERWRITE_ETHADDR_ONCE 117 #endif /* FEC_ENET */ 118 119 #define CONFIG_HOSTNAME M5373EVB 120 #define CONFIG_EXTRA_ENV_SETTINGS \ 121 "netdev=eth0\0" \ 122 "loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \ 123 "u-boot=u-boot.bin\0" \ 124 "load=tftp ${loadaddr) ${u-boot}\0" \ 125 "upd=run load; run prog\0" \ 126 "prog=prot off 0 3ffff;" \ 127 "era 0 3ffff;" \ 128 "cp.b ${loadaddr} 0 ${filesize};" \ 129 "save\0" \ 130 "" 131 132 #define CONFIG_PRAM 512 /* 512 KB */ 133 #define CONFIG_SYS_PROMPT "-> " 134 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 135 136 #ifdef CONFIG_CMD_KGDB 137 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 138 #else 139 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 140 #endif 141 142 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 143 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 144 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 145 #define CONFIG_SYS_LOAD_ADDR 0x40010000 146 147 #define CONFIG_SYS_HZ 1000 148 #define CONFIG_SYS_CLK 80000000 149 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 150 151 #define CONFIG_SYS_MBAR 0xFC000000 152 153 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 154 155 /* 156 * Low Level Configuration Settings 157 * (address mappings, register initial values, etc.) 158 * You should know what you are doing if you make changes here. 159 */ 160 /*----------------------------------------------------------------------- 161 * Definitions for initial stack pointer and data area (in DPRAM) 162 */ 163 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 164 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 165 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 166 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 167 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 168 169 /*----------------------------------------------------------------------- 170 * Start addresses for the final memory configuration 171 * (Set up by the startup code) 172 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 173 */ 174 #define CONFIG_SYS_SDRAM_BASE 0x40000000 175 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 176 #define CONFIG_SYS_SDRAM_CFG1 0x53722730 177 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 178 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 179 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 180 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 181 182 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 183 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 184 185 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 186 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 187 188 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 189 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 190 191 /* 192 * For booting Linux, the board info and command line data 193 * have to be in the first 8 MB of memory, since this is 194 * the maximum mapped by the Linux kernel during initialization ?? 195 */ 196 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 197 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 198 199 /*----------------------------------------------------------------------- 200 * FLASH organization 201 */ 202 #define CONFIG_SYS_FLASH_CFI 203 #ifdef CONFIG_SYS_FLASH_CFI 204 # define CONFIG_FLASH_CFI_DRIVER 1 205 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 206 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 207 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 208 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 209 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 210 #endif 211 212 #ifdef NANDFLASH_SIZE 213 # define CONFIG_SYS_MAX_NAND_DEVICE 1 214 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 215 # define CONFIG_SYS_NAND_SIZE 1 216 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 217 # define NAND_ALLOW_ERASE_ALL 1 218 # define CONFIG_JFFS2_NAND 1 219 # define CONFIG_JFFS2_DEV "nand0" 220 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) 221 # define CONFIG_JFFS2_PART_OFFSET 0x00000000 222 #endif 223 224 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 225 226 /* Configuration for environment 227 * Environment is embedded in u-boot in the second sector of the flash 228 */ 229 #define CONFIG_ENV_OFFSET 0x4000 230 #define CONFIG_ENV_SECT_SIZE 0x2000 231 #define CONFIG_ENV_IS_IN_FLASH 1 232 233 /*----------------------------------------------------------------------- 234 * Cache Configuration 235 */ 236 #define CONFIG_SYS_CACHELINE_SIZE 16 237 238 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 239 CONFIG_SYS_INIT_RAM_SIZE - 8) 240 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 241 CONFIG_SYS_INIT_RAM_SIZE - 4) 242 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 243 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 244 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 245 CF_ACR_EN | CF_ACR_SM_ALL) 246 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 247 CF_CACR_DCM_P) 248 249 /*----------------------------------------------------------------------- 250 * Chipselect bank definitions 251 */ 252 /* 253 * CS0 - NOR Flash 1, 2, 4, or 8MB 254 * CS1 - CompactFlash and registers 255 * CS2 - NAND Flash 16, 32, or 64MB 256 * CS3 - Available 257 * CS4 - Available 258 * CS5 - Available 259 */ 260 #define CONFIG_SYS_CS0_BASE 0 261 #define CONFIG_SYS_CS0_MASK 0x007f0001 262 #define CONFIG_SYS_CS0_CTRL 0x00001fa0 263 264 #define CONFIG_SYS_CS1_BASE 0x10000000 265 #define CONFIG_SYS_CS1_MASK 0x001f0001 266 #define CONFIG_SYS_CS1_CTRL 0x002A3780 267 268 #ifdef NANDFLASH_SIZE 269 #define CONFIG_SYS_CS2_BASE 0x20000000 270 #define CONFIG_SYS_CS2_MASK ((NANDFLASH_SIZE << 20) | 1) 271 #define CONFIG_SYS_CS2_CTRL 0x00001f60 272 #endif 273 274 #endif /* _M5373EVB_H */ 275