1 /* 2 * Configuation settings for the Freescale MCF5373 FireEngine board. 3 * 4 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5373EVB_H 15 #define _M5373EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_MCF532x /* define processor family */ 22 #define CONFIG_M5373 /* define processor type */ 23 24 #define CONFIG_MCFUART 25 #define CONFIG_SYS_UART_PORT (0) 26 #define CONFIG_BAUDRATE 115200 27 28 #undef CONFIG_WATCHDOG 29 #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ 30 31 /* Command line configuration */ 32 #include <config_cmd_default.h> 33 34 #define CONFIG_CMD_CACHE 35 #define CONFIG_CMD_DATE 36 #define CONFIG_CMD_ELF 37 #define CONFIG_CMD_FLASH 38 #define CONFIG_CMD_I2C 39 #define CONFIG_CMD_MEMORY 40 #define CONFIG_CMD_MISC 41 #define CONFIG_CMD_MII 42 #define CONFIG_CMD_NET 43 #define CONFIG_CMD_PING 44 #define CONFIG_CMD_REGINFO 45 46 #ifdef CONFIG_NANDFLASH_SIZE 47 # define CONFIG_CMD_NAND 48 #endif 49 50 #define CONFIG_SYS_UNIFY_CACHE 51 52 #define CONFIG_MCFFEC 53 #ifdef CONFIG_MCFFEC 54 # define CONFIG_MII 1 55 # define CONFIG_MII_INIT 1 56 # define CONFIG_SYS_DISCOVER_PHY 57 # define CONFIG_SYS_RX_ETH_BUFFER 8 58 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 59 60 # define CONFIG_SYS_FEC0_PINMUX 0 61 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 62 # define MCFFEC_TOUT_LOOP 50000 63 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 64 # ifndef CONFIG_SYS_DISCOVER_PHY 65 # define FECDUPLEX FULL 66 # define FECSPEED _100BASET 67 # else 68 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 69 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 70 # endif 71 # endif /* CONFIG_SYS_DISCOVER_PHY */ 72 #endif 73 74 #define CONFIG_MCFRTC 75 #undef RTC_DEBUG 76 77 /* Timer */ 78 #define CONFIG_MCFTMR 79 #undef CONFIG_MCFPIT 80 81 /* I2C */ 82 #define CONFIG_FSL_I2C 83 #define CONFIG_HARD_I2C /* I2C with hw support */ 84 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 85 #define CONFIG_SYS_I2C_SPEED 80000 86 #define CONFIG_SYS_I2C_SLAVE 0x7F 87 #define CONFIG_SYS_I2C_OFFSET 0x58000 88 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 89 90 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 91 #define CONFIG_UDP_CHECKSUM 92 93 #ifdef CONFIG_MCFFEC 94 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 95 # define CONFIG_IPADDR 192.162.1.2 96 # define CONFIG_NETMASK 255.255.255.0 97 # define CONFIG_SERVERIP 192.162.1.1 98 # define CONFIG_GATEWAYIP 192.162.1.1 99 # define CONFIG_OVERWRITE_ETHADDR_ONCE 100 #endif /* FEC_ENET */ 101 102 #define CONFIG_HOSTNAME M5373EVB 103 #define CONFIG_EXTRA_ENV_SETTINGS \ 104 "netdev=eth0\0" \ 105 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 106 "u-boot=u-boot.bin\0" \ 107 "load=tftp ${loadaddr) ${u-boot}\0" \ 108 "upd=run load; run prog\0" \ 109 "prog=prot off 0 3ffff;" \ 110 "era 0 3ffff;" \ 111 "cp.b ${loadaddr} 0 ${filesize};" \ 112 "save\0" \ 113 "" 114 115 #define CONFIG_PRAM 512 /* 512 KB */ 116 #define CONFIG_SYS_PROMPT "-> " 117 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 118 119 #ifdef CONFIG_CMD_KGDB 120 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 121 #else 122 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 123 #endif 124 125 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 126 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 127 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 128 #define CONFIG_SYS_LOAD_ADDR 0x40010000 129 130 #define CONFIG_SYS_HZ 1000 131 #define CONFIG_SYS_CLK 80000000 132 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 133 134 #define CONFIG_SYS_MBAR 0xFC000000 135 136 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 137 138 /* 139 * Low Level Configuration Settings 140 * (address mappings, register initial values, etc.) 141 * You should know what you are doing if you make changes here. 142 */ 143 /*----------------------------------------------------------------------- 144 * Definitions for initial stack pointer and data area (in DPRAM) 145 */ 146 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 147 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 148 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 149 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 150 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 151 152 /*----------------------------------------------------------------------- 153 * Start addresses for the final memory configuration 154 * (Set up by the startup code) 155 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 156 */ 157 #define CONFIG_SYS_SDRAM_BASE 0x40000000 158 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 159 #define CONFIG_SYS_SDRAM_CFG1 0x53722730 160 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 161 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 162 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 163 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 164 165 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 166 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 167 168 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 169 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 170 171 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 172 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 173 174 /* 175 * For booting Linux, the board info and command line data 176 * have to be in the first 8 MB of memory, since this is 177 * the maximum mapped by the Linux kernel during initialization ?? 178 */ 179 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 180 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 181 182 /*----------------------------------------------------------------------- 183 * FLASH organization 184 */ 185 #define CONFIG_SYS_FLASH_CFI 186 #ifdef CONFIG_SYS_FLASH_CFI 187 # define CONFIG_FLASH_CFI_DRIVER 1 188 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 189 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 190 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 191 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 192 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 193 #endif 194 195 #ifdef CONFIG_NANDFLASH_SIZE 196 # define CONFIG_SYS_MAX_NAND_DEVICE 1 197 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 198 # define CONFIG_SYS_NAND_SIZE 1 199 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 200 # define NAND_ALLOW_ERASE_ALL 1 201 # define CONFIG_JFFS2_NAND 1 202 # define CONFIG_JFFS2_DEV "nand0" 203 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) 204 # define CONFIG_JFFS2_PART_OFFSET 0x00000000 205 #endif 206 207 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 208 209 /* Configuration for environment 210 * Environment is embedded in u-boot in the second sector of the flash 211 */ 212 #define CONFIG_ENV_OFFSET 0x4000 213 #define CONFIG_ENV_SECT_SIZE 0x2000 214 #define CONFIG_ENV_IS_IN_FLASH 1 215 216 /*----------------------------------------------------------------------- 217 * Cache Configuration 218 */ 219 #define CONFIG_SYS_CACHELINE_SIZE 16 220 221 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 222 CONFIG_SYS_INIT_RAM_SIZE - 8) 223 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 224 CONFIG_SYS_INIT_RAM_SIZE - 4) 225 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 226 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 227 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 228 CF_ACR_EN | CF_ACR_SM_ALL) 229 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 230 CF_CACR_DCM_P) 231 232 /*----------------------------------------------------------------------- 233 * Chipselect bank definitions 234 */ 235 /* 236 * CS0 - NOR Flash 1, 2, 4, or 8MB 237 * CS1 - CompactFlash and registers 238 * CS2 - NAND Flash 16, 32, or 64MB 239 * CS3 - Available 240 * CS4 - Available 241 * CS5 - Available 242 */ 243 #define CONFIG_SYS_CS0_BASE 0 244 #define CONFIG_SYS_CS0_MASK 0x007f0001 245 #define CONFIG_SYS_CS0_CTRL 0x00001fa0 246 247 #define CONFIG_SYS_CS1_BASE 0x10000000 248 #define CONFIG_SYS_CS1_MASK 0x001f0001 249 #define CONFIG_SYS_CS1_CTRL 0x002A3780 250 251 #ifdef CONFIG_NANDFLASH_SIZE 252 #define CONFIG_SYS_CS2_BASE 0x20000000 253 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) 254 #define CONFIG_SYS_CS2_CTRL 0x00001f60 255 #endif 256 257 #endif /* _M5373EVB_H */ 258