1 /* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef _M5329EVB_H 31 #define _M5329EVB_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_MCF532x /* define processor family */ 38 #define CONFIG_M5329 /* define processor type */ 39 40 #undef DEBUG 41 42 #define CONFIG_MCFUART 43 #define CFG_UART_PORT (0) 44 #define CONFIG_BAUDRATE 115200 45 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 46 47 #undef CONFIG_WATCHDOG 48 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 49 50 /* Command line configuration */ 51 #include <config_cmd_default.h> 52 53 #define CONFIG_CMD_CACHE 54 #define CONFIG_CMD_DATE 55 #define CONFIG_CMD_ELF 56 #define CONFIG_CMD_FLASH 57 #define CONFIG_CMD_I2C 58 #define CONFIG_CMD_MEMORY 59 #define CONFIG_CMD_MISC 60 #define CONFIG_CMD_MII 61 #define CONFIG_CMD_NET 62 #define CONFIG_CMD_PING 63 #define CONFIG_CMD_REGINFO 64 65 #ifdef NANDFLASH_SIZE 66 # define CONFIG_CMD_NAND 67 #endif 68 69 #define CFG_UNIFY_CACHE 70 71 #define CONFIG_MCFFEC 72 #ifdef CONFIG_MCFFEC 73 # define CONFIG_NET_MULTI 1 74 # define CONFIG_MII 1 75 # define CFG_DISCOVER_PHY 76 # define CFG_RX_ETH_BUFFER 8 77 # define CFG_FAULT_ECHO_LINK_DOWN 78 79 # define CFG_FEC0_PINMUX 0 80 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE 81 # define MCFFEC_TOUT_LOOP 50000 82 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ 83 # ifndef CFG_DISCOVER_PHY 84 # define FECDUPLEX FULL 85 # define FECSPEED _100BASET 86 # else 87 # ifndef CFG_FAULT_ECHO_LINK_DOWN 88 # define CFG_FAULT_ECHO_LINK_DOWN 89 # endif 90 # endif /* CFG_DISCOVER_PHY */ 91 #endif 92 93 #define CONFIG_MCFRTC 94 #undef RTC_DEBUG 95 96 /* Timer */ 97 #define CONFIG_MCFTMR 98 #undef CONFIG_MCFPIT 99 100 /* I2C */ 101 #define CONFIG_FSL_I2C 102 #define CONFIG_HARD_I2C /* I2C with hw support */ 103 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 104 #define CFG_I2C_SPEED 80000 105 #define CFG_I2C_SLAVE 0x7F 106 #define CFG_I2C_OFFSET 0x58000 107 #define CFG_IMMR CFG_MBAR 108 109 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 110 #define CONFIG_UDP_CHECKSUM 111 112 #ifdef CONFIG_MCFFEC 113 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 114 # define CONFIG_IPADDR 192.162.1.2 115 # define CONFIG_NETMASK 255.255.255.0 116 # define CONFIG_SERVERIP 192.162.1.1 117 # define CONFIG_GATEWAYIP 192.162.1.1 118 # define CONFIG_OVERWRITE_ETHADDR_ONCE 119 #endif /* FEC_ENET */ 120 121 #define CONFIG_HOSTNAME M5329EVB 122 #define CONFIG_EXTRA_ENV_SETTINGS \ 123 "netdev=eth0\0" \ 124 "loadaddr=40010000\0" \ 125 "u-boot=u-boot.bin\0" \ 126 "load=tftp ${loadaddr) ${u-boot}\0" \ 127 "upd=run load; run prog\0" \ 128 "prog=prot off 0 2ffff;" \ 129 "era 0 2ffff;" \ 130 "cp.b ${loadaddr} 0 ${filesize};" \ 131 "save\0" \ 132 "" 133 134 #define CONFIG_PRAM 512 /* 512 KB */ 135 #define CFG_PROMPT "-> " 136 #define CFG_LONGHELP /* undef to save memory */ 137 138 #ifdef CONFIG_CMD_KGDB 139 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 140 #else 141 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 142 #endif 143 144 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 145 #define CFG_MAXARGS 16 /* max number of command args */ 146 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 147 #define CFG_LOAD_ADDR 0x40010000 148 149 #define CFG_HZ 1000 150 #define CFG_CLK 80000000 151 #define CFG_CPU_CLK CFG_CLK * 3 152 153 #define CFG_MBAR 0xFC000000 154 155 #define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000) 156 157 /* 158 * Low Level Configuration Settings 159 * (address mappings, register initial values, etc.) 160 * You should know what you are doing if you make changes here. 161 */ 162 /*----------------------------------------------------------------------- 163 * Definitions for initial stack pointer and data area (in DPRAM) 164 */ 165 #define CFG_INIT_RAM_ADDR 0x80000000 166 #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ 167 #define CFG_INIT_RAM_CTRL 0x221 168 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 169 #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10) 170 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 171 172 /*----------------------------------------------------------------------- 173 * Start addresses for the final memory configuration 174 * (Set up by the startup code) 175 * Please note that CFG_SDRAM_BASE _must_ start at 0 176 */ 177 #define CFG_SDRAM_BASE 0x40000000 178 #define CFG_SDRAM_SIZE 32 /* SDRAM size in MB */ 179 #define CFG_SDRAM_CFG1 0x53722730 180 #define CFG_SDRAM_CFG2 0x56670000 181 #define CFG_SDRAM_CTRL 0xE1092000 182 #define CFG_SDRAM_EMOD 0x40010000 183 #define CFG_SDRAM_MODE 0x018D0000 184 185 #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 186 #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) 187 188 #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) 189 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 190 191 #define CFG_BOOTPARAMS_LEN 64*1024 192 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 193 194 /* 195 * For booting Linux, the board info and command line data 196 * have to be in the first 8 MB of memory, since this is 197 * the maximum mapped by the Linux kernel during initialization ?? 198 */ 199 #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) 200 201 /*----------------------------------------------------------------------- 202 * FLASH organization 203 */ 204 #define CFG_FLASH_CFI 205 #ifdef CFG_FLASH_CFI 206 # define CFG_FLASH_CFI_DRIVER 1 207 # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ 208 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT 209 # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ 210 # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 211 # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 212 #endif 213 214 #ifdef NANDFLASH_SIZE 215 # define CFG_MAX_NAND_DEVICE 1 216 # define CFG_NAND_BASE (CFG_CS2_BASE << 16) 217 # define CFG_NAND_SIZE 1 218 # define CFG_NAND_BASE_LIST { CFG_NAND_BASE } 219 # define NAND_MAX_CHIPS 1 220 # define NAND_ALLOW_ERASE_ALL 1 221 # define CONFIG_JFFS2_NAND 1 222 # define CONFIG_JFFS2_DEV "nand0" 223 # define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1) 224 # define CONFIG_JFFS2_PART_OFFSET 0x00000000 225 #endif 226 227 #define CFG_FLASH_BASE (CFG_CS0_BASE << 16) 228 229 /* Configuration for environment 230 * Environment is embedded in u-boot in the second sector of the flash 231 */ 232 #define CFG_ENV_OFFSET 0x4000 233 #define CFG_ENV_SECT_SIZE 0x2000 234 #define CFG_ENV_IS_IN_FLASH 1 235 #define CFG_ENV_IS_EMBEDDED 1 236 237 /*----------------------------------------------------------------------- 238 * Cache Configuration 239 */ 240 #define CFG_CACHELINE_SIZE 16 241 242 /*----------------------------------------------------------------------- 243 * Chipselect bank definitions 244 */ 245 /* 246 * CS0 - NOR Flash 1, 2, 4, or 8MB 247 * CS1 - CompactFlash and registers 248 * CS2 - NAND Flash 16, 32, or 64MB 249 * CS3 - Available 250 * CS4 - Available 251 * CS5 - Available 252 */ 253 #define CFG_CS0_BASE 0 254 #define CFG_CS0_MASK 0x007f0001 255 #define CFG_CS0_CTRL 0x00001fa0 256 257 #define CFG_CS1_BASE 0x1000 258 #define CFG_CS1_MASK 0x001f0001 259 #define CFG_CS1_CTRL 0x002A3780 260 261 #ifdef NANDFLASH_SIZE 262 #define CFG_CS2_BASE 0x2000 263 #define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1) 264 #define CFG_CS2_CTRL 0x00001f60 265 #endif 266 267 #endif /* _M5329EVB_H */ 268