1 /* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5329EVB_H 15 #define _M5329EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 27 28 #define CONFIG_SYS_UNIFY_CACHE 29 30 #define CONFIG_MCFFEC 31 #ifdef CONFIG_MCFFEC 32 # define CONFIG_MII 1 33 # define CONFIG_MII_INIT 1 34 # define CONFIG_SYS_DISCOVER_PHY 35 # define CONFIG_SYS_RX_ETH_BUFFER 8 36 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 37 38 # define CONFIG_SYS_FEC0_PINMUX 0 39 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 40 # define MCFFEC_TOUT_LOOP 50000 41 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 42 # ifndef CONFIG_SYS_DISCOVER_PHY 43 # define FECDUPLEX FULL 44 # define FECSPEED _100BASET 45 # else 46 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 47 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 48 # endif 49 # endif /* CONFIG_SYS_DISCOVER_PHY */ 50 #endif 51 52 #define CONFIG_MCFRTC 53 #undef RTC_DEBUG 54 55 /* Timer */ 56 #define CONFIG_MCFTMR 57 #undef CONFIG_MCFPIT 58 59 /* I2C */ 60 #define CONFIG_SYS_I2C 61 #define CONFIG_SYS_I2C_FSL 62 #define CONFIG_SYS_FSL_I2C_SPEED 80000 63 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 64 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 65 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 66 67 #define CONFIG_UDP_CHECKSUM 68 69 #ifdef CONFIG_MCFFEC 70 # define CONFIG_IPADDR 192.162.1.2 71 # define CONFIG_NETMASK 255.255.255.0 72 # define CONFIG_SERVERIP 192.162.1.1 73 # define CONFIG_GATEWAYIP 192.162.1.1 74 #endif /* FEC_ENET */ 75 76 #define CONFIG_HOSTNAME M5329EVB 77 #define CONFIG_EXTRA_ENV_SETTINGS \ 78 "netdev=eth0\0" \ 79 "loadaddr=40010000\0" \ 80 "u-boot=u-boot.bin\0" \ 81 "load=tftp ${loadaddr) ${u-boot}\0" \ 82 "upd=run load; run prog\0" \ 83 "prog=prot off 0 3ffff;" \ 84 "era 0 3ffff;" \ 85 "cp.b ${loadaddr} 0 ${filesize};" \ 86 "save\0" \ 87 "" 88 89 #define CONFIG_PRAM 512 /* 512 KB */ 90 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 91 92 #define CONFIG_SYS_LOAD_ADDR 0x40010000 93 94 #define CONFIG_SYS_CLK 80000000 95 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 96 97 #define CONFIG_SYS_MBAR 0xFC000000 98 99 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 100 101 /* 102 * Low Level Configuration Settings 103 * (address mappings, register initial values, etc.) 104 * You should know what you are doing if you make changes here. 105 */ 106 /*----------------------------------------------------------------------- 107 * Definitions for initial stack pointer and data area (in DPRAM) 108 */ 109 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 110 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 111 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 112 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 113 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 114 115 /*----------------------------------------------------------------------- 116 * Start addresses for the final memory configuration 117 * (Set up by the startup code) 118 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 119 */ 120 #define CONFIG_SYS_SDRAM_BASE 0x40000000 121 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 122 #define CONFIG_SYS_SDRAM_CFG1 0x53722730 123 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 124 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 125 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 126 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 127 128 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 129 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 130 131 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 132 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 133 134 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 135 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 136 137 /* 138 * For booting Linux, the board info and command line data 139 * have to be in the first 8 MB of memory, since this is 140 * the maximum mapped by the Linux kernel during initialization ?? 141 */ 142 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 143 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 144 145 /*----------------------------------------------------------------------- 146 * FLASH organization 147 */ 148 #define CONFIG_SYS_FLASH_CFI 149 #ifdef CONFIG_SYS_FLASH_CFI 150 # define CONFIG_FLASH_CFI_DRIVER 1 151 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 152 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 153 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 154 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 155 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 156 #endif 157 158 #ifdef CONFIG_NANDFLASH_SIZE 159 # define CONFIG_SYS_MAX_NAND_DEVICE 1 160 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 161 # define CONFIG_SYS_NAND_SIZE 1 162 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 163 # define NAND_ALLOW_ERASE_ALL 1 164 # define CONFIG_JFFS2_NAND 1 165 # define CONFIG_JFFS2_DEV "nand0" 166 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) 167 # define CONFIG_JFFS2_PART_OFFSET 0x00000000 168 #endif 169 170 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 171 172 /* Configuration for environment 173 * Environment is embedded in u-boot in the second sector of the flash 174 */ 175 #define CONFIG_ENV_OFFSET 0x4000 176 #define CONFIG_ENV_SECT_SIZE 0x2000 177 178 #define LDS_BOARD_TEXT \ 179 . = DEFINED(env_offset) ? env_offset : .; \ 180 env/embedded.o(.text*); 181 182 /*----------------------------------------------------------------------- 183 * Cache Configuration 184 */ 185 #define CONFIG_SYS_CACHELINE_SIZE 16 186 187 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 188 CONFIG_SYS_INIT_RAM_SIZE - 8) 189 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 190 CONFIG_SYS_INIT_RAM_SIZE - 4) 191 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 192 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 193 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 194 CF_ACR_EN | CF_ACR_SM_ALL) 195 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 196 CF_CACR_DCM_P) 197 198 /*----------------------------------------------------------------------- 199 * Chipselect bank definitions 200 */ 201 /* 202 * CS0 - NOR Flash 1, 2, 4, or 8MB 203 * CS1 - CompactFlash and registers 204 * CS2 - NAND Flash 16, 32, or 64MB 205 * CS3 - Available 206 * CS4 - Available 207 * CS5 - Available 208 */ 209 #define CONFIG_SYS_CS0_BASE 0 210 #define CONFIG_SYS_CS0_MASK 0x007f0001 211 #define CONFIG_SYS_CS0_CTRL 0x00001fa0 212 213 #define CONFIG_SYS_CS1_BASE 0x10000000 214 #define CONFIG_SYS_CS1_MASK 0x001f0001 215 #define CONFIG_SYS_CS1_CTRL 0x002A3780 216 217 #ifdef CONFIG_NANDFLASH_SIZE 218 #define CONFIG_SYS_CS2_BASE 0x20000000 219 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) 220 #define CONFIG_SYS_CS2_CTRL 0x00001f60 221 #endif 222 223 #endif /* _M5329EVB_H */ 224